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Electronic digital logic circuitry November USPTO class listing 11/08

20080290893 - Local clock buffer (lcb) with asymmetric inductive peaking: A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080290894 - On die termination (odt) circuit having improved high frequency performance: An On Die Termination (ODT) circuit for performing an ODT operation. The ODT circuit includes a resistor having a first end to receive an ODT enable signal; and a switch unit coupled to a second end of the resistor. The ODT operation is performed in response to the ODT enable... Agent: Marger Johnson & Mccollom, P.C.

20080290896 - System and method for dynamically executing a function in a programmable logic array: A reconfigurable logic array (RLA) system that includes an RLA and a programmer for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks. The programmer contains software that partitions the RLA into... Agent: Downs Rachlin Martin PLLC

20080290895 - System and method for local generation of programming data in a programable device: An apparatus for and method of programming a programmable logic device, the programmable logic device comprising a plurality of serially connected programmable logic regions. The method comprises the steps of receiving initial programming data for programming the plurality of serially connected programmable logic regions and receiving transformation data related to... Agent: Greenblum & Bernstein, P.L.C

20080290898 - Programmable logic device having complex logic blocks with improved logic cell functionality: A CLB-based PLD with logic cells having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has... Agent: Weaver Austin Villeneuve & Sampson LLP - Altera Attn: Altera

20080290897 - Programmable logic device having logic modules with improved register capabilities: A PLD that has more flip flops per logic module by providing more registered outputs than combinational outputs; and/or a combinational output that can drive more than one register is disclosed. The PLD includes a plurality of logic array blocks arranged in an array and a plurality of inter-logic array... Agent: Weaver Austin Villeneuve & Sampson LLP - Altera Attn: Altera

20080290899 - Integrated circuit and method of detecting a signal edge transition: The invention relates to an edge transition detector, and a method of operating an edge transition detector. An integrated circuit includes an edge transition detector for producing an output signal at an output node in response to an input signal. The edge transition detector includes a switch coupled to the... Agent: Slater & Matsil LLP

20080290902 - Level converter: A level converter comprising an input circuit, coupled to a low power source and a first high power source, which generates a complementary first signal and second signal; and a shift circuit that outputs an output signal generated by shifting a voltage level of the input signal, the shift circuit... Agent: Arent Fox LLP

20080290900 - Two-stage level shifting module: For raising low voltage levels of a voltage range without over-broadening the voltage range, a first stage voltage level shifting circuit, which is capable of raising an upper bound of its input voltage range, is coupled to a second voltage level shifting circuit, which is capable of raising both an... Agent: North America Intellectual Property Corporation

20080290901 - Voltage shifter circuit: The present invention provides a voltage shifter circuit, in which a control circuit is used to control the pull-up circuit, so that the pull-up circuit is kept as off when the signal from the input signal source changes from a low voltage to a high voltage. Hence, the competition between... Agent: Squire, Sanders & Dempsey L.L.P.

20080284463 - programmable circuit having a carbon nanotube: A semiconductor device comprising a programming circuit that includes an active device on or in a substrate and a programmable electronic component on the substrate. The programmable electronic component includes at least one carbon nanotube having a segment with an adjusted diameter. The programmable electronic component has a value that... Agent: Texas Instruments Incorporated

20080284464 - Time based driver output transition (slew) rate compensation: Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired... Agent: Greenblum & Bernstein, P.L.C

20080284466 - Driver circuit: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a... Agent: Ibm Corporation, T.j. Watson Research Center

20080284467 - On die termination circuit and method for calibrating the same: On die termination circuit and method for calibrating the same includes a external resistor connected to a first node, a plurality of calibration resistors connected to a second node, the plurality of calibration resistors being turned on/off in response to a calibration code set, a current mirror configured to mirror... Agent: Mcdermott Will & Emery LLP

20080284465 - On-die system and method for controlling termination impedance of memory device data bus terminals: A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080284468 - Method and apparatus for controlling a communication signal by monitoring one or more voltage sources: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20080284469 - Reduced power consumption limited-switch dynamic logic (lsdl) circuit: An limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080278191 - Leakage power management with ndr isolation devices: A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the... Agent: Silicon Valley Patent Group LLP

20080278192 - Data output driving circuit for a semiconductor apparatus: A data output driving circuit for a semiconductor apparatus includes a code converter that varies an input on-die termination code according to a control signal and outputs the code, and a driver block having impedance which can be modified according to the code generated by the code converter.... Agent: Baker & Mckenzie LLP Patent Department

20080278193 - Reference voltage generators for reducing and/or eliminating termination mismatch: A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits... Agent: Lee & Morse, P.C.

20080278194 - Semiconductor integrated circuit and operation method of the same: A semiconductor integrated circuit including on the same semiconductor substrate: a first circuit block including a switching transistor which is off when the first circuit block is inactive and on when the first circuit block is active, the first circuit block including internal circuits adapted to provide predetermined functions, the... Agent: Rader Fishman & Grauer PLLC

20080278196 - Logic circuits having dynamically configurable logic gate arrays: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20080278197 - Programmable logic device with embedded switch fabric: The invention in the simplest form is a programmable logic device consisting of gate arrays, external I/O endpoints, and an embedded switch fabric configurable for connecting gates to gates, endpoints to endpoints and gates to endpoints. The architecture may employ a fabric interface of non-blocking crossbar switches for making complex... Agent: Vern Maine & Associates

20080278195 - Structure for executing software within real-time hardware constraints using functionally programmable branch table: A computer system is disclosed which includes a design structure including a CPU or microprocessor to drive tightly constrained hardware events. The system comprises a processor having a set of system inputs to drive a functionally programmable event, and a fast branch in the CPU including a state handler to... Agent: Scully, Scott, Murphy & Presser, P.C.

20080278198 - Buffer for object information: A buffer that is state-aware and/or node-oriented. In a state-aware buffer, one or more operations relating to a state can be performed. In a node-oriented buffer, instances of a node can be accessed without regard to an object structure in which the instance is included.... Agent: Fish & Richardson, P.C.

20080278199 - Off-chip driver: A driver includes a plurality of first PMOS transistors, a first resistor, a amplifier, a second PMOS transistor and a second resistor. The amplifier herein receives a reference voltage and outputs a regulating voltage. The above-mentioned reference voltage is produced in accordance with a band-gap reference voltage. Since the band-gap... Agent: Jianq Chyun Intellectual Property Office

20080272799 - Electronic device: An electronic device comprising at least one input/output circuit (10) in a first supply voltage domain (VDD, GND) is provided. The electronic device furthermore comprises a buffer (INV) which is coupled to the input/output circuit for driving an input of the input/output circuit (10). The buffer comprises a first and... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080272800 - Dynamic dual control on-die termination: Controlling on-die termination on a bi-directional single-ended data bus carrying data between a controller and a memory device. The controller and the memory device respectively include input termination pull-ups and input termination pull-downs. An enabled state is maintained for the input termination pull-downs of the controller except when data is... Agent: Rader Fishman & Grauer PLLC

20080272804 - Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an fpga: A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed... Agent: Lewis And Roca LLP

20080272802 - Random access of user design states in a configurable ic: Some embodiments of the invention is a configurable integrated circuit (IC) that includes (1) several configurable logic circuits, (2) a first routing network for connecting the configurable logic circuits, (3) several user design state (UDS) circuits, and (4) a second network communicatively coupled to the UDS circuits. In least one... Agent: Adeli & Tollen, LLP

20080272801 - Runtime loading of configuration data in a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While... Agent: Adeli & Tollen, LLP

20080272803 - System-on-a-chip integrated circuit including dual-function analog and digital inputs: An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture programmably coupling selected ones of the plurality of inputs, the plurality... Agent: Lewis And Roca LLP

20080272805 - Method and apparatus for boundary scan programming of memory devices: In accordance with at least one embodiment, a method, apparatus, and article of manufacture are provided for configuring a virtual boundary register in a programmable logic device (PLD), transmitting a first user-definable-command operation code (opcode) to the PLD to effect programming of a memory device coupled to the PLD, and... Agent: Ross D. Snyder & Associates, Inc.

20080272806 - Scalable non-blocking switching network for programmable logic: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications,... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080272807 - Thin film logic device and system: Thin film logic circuits employ thin-film switching devices to execute complementary logic functions. Such logic devices operate, as complementary metal oxide semiconductor (CMOS) logic devices do, in a manner that does not provide a direct conduction path between a system supply and a system return. Complementary logic circuits may employ... Agent: Ovonyx, Inc