Electronic digital logic circuitry patents - Monitor Patents
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Electronic digital logic circuitry October patent listing 10/08

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
10/23/2008 > patent applications in patent subcategories. patent listing

20080258753 - Systems, methods and apparatus for anti-symmetric qubit-coupling: Apparatus, articles and methods relate to anti-symmetric superconducting devices for coupling superconducting qubits.... Agent: Seed Intellectual Property Law Group PLLC

20080258754 - Security element for an integrated circuit, integrated circuit including the same, and method for securing an integrated circuit: An integrated circuit including a substrate; a circuit pattern formed over the substrate; and one or more fences formed around edges of the circuit pattern, each of the one or more fences having a determined electrical resistance which is used to detect the addition of malicious circuitry. Each fence has... Agent: Amster, Rothstein & Ebenstein LLP

20080258755 - Noise reduction among conductors: Noise reduction among conductors, the conductors disposed adjacent to one another, the conductors characterized as two or more aggressor conductors and one or more victim conductors, a least two of the aggressor conductors driven with at least two signals that induce unwanted crosstalk upon at least one of the victim... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20080258756 - Semiconductor apparatus: The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON... Agent: Foley And Lardner LLP Suite 500

20080258762 - Asics having programmable bypass of design faults: A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to... Agent: Macpherson Kwok Chen & Heid LLP

20080258758 - Embedded system and control method therefor: An embedded system having a programmable logic circuit, a plurality of storage devices each storing configuration data defining circuit information of the logic circuit, a setting information storage storing setting information including information of a storage device storing the configuration data and a controller selecting one of the plurality of... Agent: Staas & Halsey LLP

20080258757 - Integrated circuit feature definition using one-time-programmable (otp) memory: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing... Agent: Mendelsohn & Associates, P.C.

20080258761 - Runtime loading of configuration data in a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While... Agent: Adeli & Tollen, LLP

20080258760 - System level interconnect with programmable switching: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A... Agent: Stolowitz Ford Cowger, LLP/cypress

20080258759 - Universal digital block interconnection and channel routing: A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable... Agent: Stolowitz Ford Cowger, LLP/cypress

20080258763 - Block symmetrization in a field programmable gate array: An FPGA architecture has top, middle and low levels. The top level is an array of B 16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing... Agent: Lewis And Roca LLP

20080258764 - Interconnect structure enabling indirect routing in programmable logic: An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the... Agent: Sadler, Breen, Morasch & Colby, Ps

20080258765 - Low-power transceiver architectures for programmable logic integrated circuit devices: High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In... Agent: Ropes & Gray LLP

20080258767 - Computational nodes and computational-node networks that include dynamical-nanodevice connections: Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected... Agent: Hewlett Packard Company

20080258766 - Mixed signal integrated circuit: This invention relates to mixed signal integrated circuits, that is, integrated circuits comprising both analogue and digital circuitry. More particularly, it concerns reduction of noise in such a device. When a digital circuit is included in the same integrated circuit device as an analogue circuit, the digital circuit may be... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258768 - Method and circuit for controlling pin capacitance in an electronic device: A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed... Agent: Stephen A. Gratton

20080258769 - Tri-state circuit element plus tri-state-multiplexer circuitry: A Tri-State circuit element (100) composed of Complementary Metal Oxide Semiconductor (CMOS)—devices is described. Said Tri-State circuit element (100) having a data signal input terminal (102) for receiving a data signal, an enable signal input terminal (104) for receiving an enable signal, and an output signal terminal (106) for providing... Agent: International Business Machines Corporation

20080258770 - Single threshold and single conductivity type logic: A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258772 - Clock signal networks for structured asic devices: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of... Agent: Ropes & Gray LLP

20080258771 - Semiconductor integrated circuit device: A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors being connected in series between a first power supply line and a first substrate well provided on the semiconductor substrate, the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258773 - Universal logic gate utilizing nanotechnology: A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create A plasticity mechanism is also provided, which is based on a plasticity rule for... Agent: Attn: Kermit D. Lopez Ortiz & Lopez, PLLC

20080258774 - Semiconductor device with a logic circuit: The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The... Agent: Foley And Lardner LLP Suite 500

20080258775 - Nand/nor registers: A register receives an input signal and provides output signals that represent true complementary logic values of the input signal. One implementation of the register includes: a first stage circuit and a second stage circuit. After the output signals are derived, the second stage circuit provides feedback signals to block... Agent: Brooks Kushman P.C. / Sun / Stk

  
10/23/2008 > patent applications in patent subcategories. patent listing

20080258753 - Systems, methods and apparatus for anti-symmetric qubit-coupling: Apparatus, articles and methods relate to anti-symmetric superconducting devices for coupling superconducting qubits.... Agent: Seed Intellectual Property Law Group PLLC

20080258754 - Security element for an integrated circuit, integrated circuit including the same, and method for securing an integrated circuit: An integrated circuit including a substrate; a circuit pattern formed over the substrate; and one or more fences formed around edges of the circuit pattern, each of the one or more fences having a determined electrical resistance which is used to detect the addition of malicious circuitry. Each fence has... Agent: Amster, Rothstein & Ebenstein LLP

20080258755 - Noise reduction among conductors: Noise reduction among conductors, the conductors disposed adjacent to one another, the conductors characterized as two or more aggressor conductors and one or more victim conductors, a least two of the aggressor conductors driven with at least two signals that induce unwanted crosstalk upon at least one of the victim... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20080258756 - Semiconductor apparatus: The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON... Agent: Foley And Lardner LLP Suite 500

20080258762 - Asics having programmable bypass of design faults: A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to... Agent: Macpherson Kwok Chen & Heid LLP

20080258758 - Embedded system and control method therefor: An embedded system having a programmable logic circuit, a plurality of storage devices each storing configuration data defining circuit information of the logic circuit, a setting information storage storing setting information including information of a storage device storing the configuration data and a controller selecting one of the plurality of... Agent: Staas & Halsey LLP

20080258757 - Integrated circuit feature definition using one-time-programmable (otp) memory: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing... Agent: Mendelsohn & Associates, P.C.

20080258761 - Runtime loading of configuration data in a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While... Agent: Adeli & Tollen, LLP

20080258760 - System level interconnect with programmable switching: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A... Agent: Stolowitz Ford Cowger, LLP/cypress

20080258759 - Universal digital block interconnection and channel routing: A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable... Agent: Stolowitz Ford Cowger, LLP/cypress

20080258763 - Block symmetrization in a field programmable gate array: An FPGA architecture has top, middle and low levels. The top level is an array of B 16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing... Agent: Lewis And Roca LLP

20080258764 - Interconnect structure enabling indirect routing in programmable logic: An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the... Agent: Sadler, Breen, Morasch & Colby, Ps

20080258765 - Low-power transceiver architectures for programmable logic integrated circuit devices: High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In... Agent: Ropes & Gray LLP

20080258767 - Computational nodes and computational-node networks that include dynamical-nanodevice connections: Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected... Agent: Hewlett Packard Company

20080258766 - Mixed signal integrated circuit: This invention relates to mixed signal integrated circuits, that is, integrated circuits comprising both analogue and digital circuitry. More particularly, it concerns reduction of noise in such a device. When a digital circuit is included in the same integrated circuit device as an analogue circuit, the digital circuit may be... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258768 - Method and circuit for controlling pin capacitance in an electronic device: A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed... Agent: Stephen A. Gratton

20080258769 - Tri-state circuit element plus tri-state-multiplexer circuitry: A Tri-State circuit element (100) composed of Complementary Metal Oxide Semiconductor (CMOS)—devices is described. Said Tri-State circuit element (100) having a data signal input terminal (102) for receiving a data signal, an enable signal input terminal (104) for receiving an enable signal, and an output signal terminal (106) for providing... Agent: International Business Machines Corporation

20080258770 - Single threshold and single conductivity type logic: A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258772 - Clock signal networks for structured asic devices: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of... Agent: Ropes & Gray LLP

20080258771 - Semiconductor integrated circuit device: A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors being connected in series between a first power supply line and a first substrate well provided on the semiconductor substrate, the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258773 - Universal logic gate utilizing nanotechnology: A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create A plasticity mechanism is also provided, which is based on a plasticity rule for... Agent: Attn: Kermit D. Lopez Ortiz & Lopez, PLLC

20080258774 - Semiconductor device with a logic circuit: The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The... Agent: Foley And Lardner LLP Suite 500

20080258775 - Nand/nor registers: A register receives an input signal and provides output signals that represent true complementary logic values of the input signal. One implementation of the register includes: a first stage circuit and a second stage circuit. After the output signals are derived, the second stage circuit provides feedback signals to block... Agent: Brooks Kushman P.C. / Sun / Stk

  
10/16/2008 > patent applications in patent subcategories. patent listing

20080252331 - Device for defeating reverse engineering of integrated circuits by optical means: A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20080252333 - Resistor circuit, interface circuit including resistor circuit, and electronic instrument: A resistor circuit includes n-stage unit circuits, each of which includes a first resistor element provided between first and second terminals, a first disconnection element provided between the second and third terminals, and a second disconnection element and a second resistor element provided in series between the second and fourth... Agent: Harness, Dickey & Pierce, P.L.C

20080252332 - Semiconductor integrated circuit and method of controlling the same: A semiconductor integrated circuit includes an ODT signal generator that receives an ODT command signal, an ODT reset signal, and an ODT calibration end signal to generate an ODT control signal according to the phase of the ODT calibration end signal, and an ODT resistance adjusting unit that is to... Agent: Baker & Mckenzie LLP Patent Department

20080252334 - Adding or subtracting inputs using a carry signal with a fixed value of logic 0: A configurable logic device configured to add or subtract inputs using a carry signal with a fixed value of 0 is described. In embodiment(s), inputs are received by a device. The device is configured to add or subtract the inputs using a carry signal that has a fixed value of... Agent: Sadler, Breen, Morasch & Colby, Ps

20080252335 - Robust and economic solution for fpga bitfile upgrade: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files... Agent: O2micro Inc C/o Murabito, Hao & Barnes LLP

  
10/09/2008 > patent applications in patent subcategories. patent listing

20080246509 - Power-on-reset circuitry: Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process... Agent: G. Victor Treyz

20080246510 - Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks: A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a... Agent: Lewis And Roca LLP

20080246511 - Differential drive circuit and electronic apparatus incorporating the same: A differential driving circuit used for low voltage differential signals and an electronic device incorporating the same are provided wherein no differential amplifiers are used or the number of differential amplifiers are reduced, thereby reducing the circuit area and the current consumption and further solving the problem of oscillation caused... Agent: Cook Alex Ltd

20080246513 - Gate driving circuit: The present invention relates to a gate driving circuit, comprising a driver control circuit, a voltage following bias circuit, a pull up circuit and a MOS transistor. The driver control circuit receives an active signal and generates a pull up signal or a pull down signal. In case of the... Agent: Rosenberg, Klein & Lee

20080246512 - Slew-rate controlled pad driver in digital cmos process using parasitic device cap: A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node. A PMOS pull-up transistor is provided, having a source connected to one side of a power supply, having a gate, and having a drain connected to... Agent: Texas Instruments Incorporated

20080246514 - Decoder circuit: A decoder circuit that selects a grayscale voltage responsive to digital input includes a first transistor circuit that selects grayscale voltages greater than a certain voltage and a second transistor circuit that selects grayscale voltages less than the certain voltage. The two transistor circuits are formed in separate substrates, one... Agent: Volentine & Whitt PLLC

  
10/02/2008 > patent applications in patent subcategories. patent listing

20080238472 - Low power mode fault recovery method, system and apparatus: A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes... Agent: Attention: Paul N. Katz Baker Botts L.L.P.

20080238474 - Booster circuits for reducing latency: A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney, LLP

20080238473 - Push-pull pulse register circuit: A push-pull pulse register circuit. The push-pull pulse register circuit includes a first logic inverter having first-inverter input and first-inverter output, a second logic inverter having second-inverter input and second-inverter output, a third logic inverter having third-inverter input and third-inverter output and configured to receive logic input data at the... Agent: Stmicroelectronics, Inc.

20080238475 - Software programmable logic using spin transfer torque magnetoresistive random access memory: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that... Agent: Qualcomm Incorporated

20080238476 - Configurable time borrowing flip-flops: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second... Agent: G. Victor Treyz

20080238478 - Fpga architecture at conventonal and submicron scales: Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input... Agent: Hewlett Packard Company

20080238477 - Tileable field-programmable gate array architecture: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals,... Agent: Lewis And Roca LLP

20080238480 - Reversible sequential apparatuses: A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first... Agent: Wpat, PC Intellectual Property Attorneys

20080238479 - Reversible sequential element and reversible sequential circuit thereof: A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal.... Agent: Wpat, PC Intellectual Property Attorneys

20080238481 - Level shift circuit: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an... Agent: Mcdermott Will & Emery LLP

20080238482 - Transmitter swing control circuit and method: disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.... Agent: Intel Corporation C/o Intellevate, LLC

20080238483 - Reduced-delay clocked logic: Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle. The partially determined next state of the clocked logic circuit is prevented from... Agent: Coats & Bennett/qimonda

20080238484 - Local clock buffer (lcb) with asymmetric inductive peaking: A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080238485 - Semiconductor integrated circuit device: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080238486 - Semiconductor integrated circuit device, semiconductor integrated circuit design method, and semiconductor integrated circuit design apparatus: A semiconductor integrated circuit design method includes a step (L) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (P) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route... Agent: Mcdermott Will & Emery LLP

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