Electronic digital logic circuitry inventions 09/08

20080231313 - Semiconductor device: A semiconductor device according to the present invention includes an internal circuit executing a predetermined processing based on signal input from an external device, an output buffer driving line connected to an output terminal based on signal output from the internal circuit, a feedback line branched off from signal line... Agent: Mcginn Intellectual Property Law Group, PLLC

20080231314 - Configurable ic having a routing fabric with storage elements: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing... Agent: Adeli & Tollen, LLP

20080231315 - Configurable ic having a routing fabric with storage elements: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing... Agent: Adeli & Tollen, LLP

20080231316 - Distributed memory in field-programmable gate array integrated circuit devices: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used... Agent: Ropes & Gray LLP

20080231318 - Configurable ic having a routing fabric with storage elements: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing... Agent: Adeli & Tollen, LLP

20080231319 - Dedicated input/output first in/first out module for a field programmable gate array: A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to... Agent: Lewis And Roca LLP

20080231317 - Staggered logic array block architecture: A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of LABs substantially aligned with each other and coupled to the first group of LABs by a plurality of... Agent: Ropes & Gray LLP

20080231320 - Tri-state circuit using nanotube switching elements: Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tri-stated, which state allows interconnection to a common bus or other shared communication lines.... Agent: Wilmerhale/boston

20080231321 - Drive circuit with a top level shifter for transmission of an input signal, and method for transmission: A TOP level switch for use in a drive circuit in power-electronic systems having a half-bridge circuit formed by two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged connected in series. The TOP level shifter transmits an input signal from drive logic... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20080231322 - Circuit device and method of controlling a voltage swing: In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path... Agent: Qualcomm Incorporated

20080231323 - Integrated circuit chip with improved array stability: A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g.,... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080224726 - Quasi-particle interferometry for logical gates: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for ν=5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we... Agent: Woodcock Washburn LLP (microsoft Corporation)

20080224727 - Logic system for dpa and/or side channel attach resistance: DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create... Agent: Knobbe Martens Olson & Bear LLP

20080224728 - On-die termination circuit of semiconductor memory apparatus: An on-die termination circuit of a semiconductor memory apparatus includes a comparator that compares a voltage corresponding to a normal code with a reference voltage to output a comparison signal. A code adjusting unit varies the normal code according to the comparison signal, outputs the varied normal code, and resets... Agent: Venable LLP

20080224729 - Integrated circuits with reduced leakage current: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled... Agent: Jonathan W. Hallman Macpherson Kwok Chen & Heid LLP

20080224730 - Configuration network for a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments,... Agent: Adeli & Tollen, LLP

20080224731 - Non-volatile memory architecture for programmable-logic-based system on a chip: A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled to the programmable logic block. A JTAG port is... Agent: Lewis And Roca LLP

20080224732 - Logic modules for semiconductor integrated circuits: A logic module (400) that is capable of implementing data-path and random logic (command Z in block 42) uses control logic for selectively coupling one or more of the input terminals (10, 12, 14, 16, 18, 40) to the at least one output terminal (20). The control logic comprises a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080224733 - Electronic circuit for maintaining and controlling data bus state: The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus... Agent: Scully, Scott, Murphy & Presser, P.C.

20080224734 - Multi-terminal chalcogenide logic circuits: In one embodiment, the circuits include one or more input terminals, one or more output terminals, and a clock terminal. The input terminals receive one or more input signals and deliver them to the circuit for processing according to a logic operation. Upon conclusion of processing, the output of the... Agent: Energy Conversion Devices, Inc.

20080218196 - System and method for protecting data based on geographic presence of a restricted device: A method of protecting data stored by an electronic device includes determining an identity of a restricted device. Also determined is the identity of restricted data associated with the restricted device, the restricted data being one or more items of data stored by the electronic device. Data protection for the... Agent: Warren A. Sklar (soer) Renner, Otto, Boisselle & Sklar, LLP

20080218197 - Programmable logic device having redundancy with logic element granularity: A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines interconnecting the LABs of the array. Each of the LABs further includes a predetermined number of logic elements and redundancy... Agent: Weaver Austin Villeneuve & Sampson LLP - Altera Attn: Altera

20080218198 - Semiconductor integrated circuit: It is made possible to detect degradation in a circuit before an operation fault will occur. A semiconductor integrated circuit includes: a circuit to be tested; a plurality of logical circuits which have different logical thresholds and which perform operation on an output of the circuit to be tested, on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080218199 - Output level stabilization circuit and cml circuit using the same: An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which... Agent: Sughrue Mion, Pllc

20080218201 - Cml delay cell with linear rail-to-rail tuning range and constant output swing: A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a... Agent: Cantor Colburn LLP - Ibm Research Triangle Park

20080218200 - Organic tft inverter arrangement: An organic TFT (OTFT) inverter arrangement comprises an inverter stage including a series arrangement of first and second MOS OTFTs (T1, T2) connected between first and second supply terminals (VDD), the first and second OTFTs having first and second gates, respectively. An input terminal (VIN) is connected to the first... Agent: Oliff & Berridge, Plc

20080218204 - Method of configuring embedded application-specific functional blocks: A method of configuring application-specific functional blocks embedded in a user programmable fabric, the user programmable fabric comprising configuration data control means having an input and an output and the application-specific functional blocks comprising configuration memory means having an input and an output. The method comprises the steps of sending... Agent: Greenblum & Bernstein, P.L.C

20080218203 - Programmable logic integrated circuit for digital algorithmic functions: A programmable integrated circuit for calculating a digital algorithm is disclosed. The integrated circuit is programmable to operate on input data in accordance with one or more predetermined digital algorithms.... Agent: Donald J Lenkszus

20080218202 - Reconfigurable array to compute digital algorithms: An integrated circuit comprising a reconfigurable arrangement to compute digital algorithms by operating on digital data is described.... Agent: Donald J Lenkszus

20080218205 - Timing exact design conversions from fpga to asic: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor... Agent: Raminda U. Madurawe

20080218206 - Field programmable gate array long line routing network: A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of... Agent: Lewis And Roca LLP

20080218207 - Synchronous first-in/first-out block memory for a field programmable gate array: The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random... Agent: Lewis And Roca LLP

20080218208 - Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks: A PLD with LAB interconnect lines that span adjacent LABs in the array and that have the ability to interconnect two logic elements in the different LABs. The PLD includes a plurality of LABs arranged in an array and a plurality of inter-LAB lines interconnecting the LABs of the array.... Agent: Weaver Austin Villeneuve & Sampson LLP - Altera Attn: Altera

20080218209 - Device for controlling terminal state, method thereof, and device for transmitting paging message: The present invention relates to a device for controlling a state of a terminal with respect to mobility management, and a method thereof. The state of the terminal includes a disconnected state and a connected state, the connected state includes an active state and an idle state, and the active... Agent: Cantor Colburn, LLP

20080218211 - High-speed buffer circuit, system and method: A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including... Agent: Stmicroelectronics, Inc.

20080218210 - Integrated nanotube and field effect switching devices: Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes... Agent: Wilmerhale/boston

20080218212 - Low to high voltage conversion output driver: A low to high voltage conversion output driver. The low to high voltage conversion output driver has an output coupled to a first fixed voltage via a load device and comprises a current source, a low voltage transistor, and a high voltage transistor. The current source has one end coupled... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080218213 - Bidirectional level shift circuit and bidirectional bus system: A plurality of transistors are connected between an I2C bus operating at a first voltage level and an I2C bus operating at a second voltage level and a main control electrode of at least one transistor is connected to a first power supply terminal and a main control electrode of... Agent: Ratnerprestia

20080218214 - Semiconductor output circuit, external output signal generation method, and semiconductor device: A semiconductor output circuit, an external output signal generation method and a semiconductor device that suppress variation in an external output signal caused by a decrease in power supply voltage. An output section changes electric potential of an external output signal EB according to a change in electric potential of... Agent: Arent Fox LLP

20080218215 - Advanced repeater utilizing signal distribution delay: An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coupled to said output signal line for changing state... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20080211532 - Circuit with control function and test method thereof: There is provided a circuit with control function including a circuit to be controlled so as to be operated only if a predetermined environment meets a specific condition and being arranged to detect, in any predetermined environment, whether or not the circuit with control function is normally operated, and a... Agent: Oliff & Berridge, PLC

20080211536 - Driver calibration methods and circuits: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify... Agent: Silicon Edge Law Group, LLP

20080211533 - Impedance matching circuit and semiconductor memory device with the same: An impedance matching circuit includes a code generating unit for generating a calibration code in response to a reference voltage and a voltage on a node, a calibration resistance unit for supplying a power supply voltage to the node, being calibrated to an external resistor, wherein the calibration resistance unit... Agent: Rabin & Berdo, PC

20080211534 - Impedance matching circuit and semiconductor memory device with the same: An impedance matching circuit of a semiconductor memory device performs a ZQ calibration with initial values that reflect an offset error according to variations in a manufacturing process. The impedance matching circuit includes a first pull-down resistance unit, a first pull-up resistance unit, and a code generation unit. The first... Agent: Rabin & Berdo, PC

20080211535 - Pseudo-differential output driver with high immunity to noise and jitter: Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two differential input signals and outputs a single output signal with low voltage transistors and programmable impedance and on-die termination circuits. The pseudo-differential output... Agent: Ropes & Gray LLP

20080211537 - Open drain output circuit: The transition time of an output is sometimes changed by a certain supply voltage connected to an output terminal of an output circuit. An output circuit to address this problem includes: a level detection circuit which detects a pull-up supply voltage applied to an output terminal OUT; and an open... Agent: Mcginn Intellectual Property Law Group, PLLC

20080211538 - Flexible wrapper architecture for tiled networks on a chip: A wrapper organization and architecture for networks on a chip employing an optimized switch arrangement with virtual output queuing and a backpressure mechanism for congestion control.... Agent: Brosemer, Kolefas & Associates, LLC (necl)

20080211539 - Programmable matrix array with phase-change material: A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The... Agent: Ovonyx, Inc

20080211540 - Programmable anti-fuse based on, e.g., zncds memory devices for fpga and other applications: According to some embodiments, an “excess-current programming method” on ZnCdS memory devices for FPGA applications is disclosed. an “excess-current programming method” can also be employed within a variety of other applications, including other memory devices having low On-resistance, such as, e.g., metal-oxide memory like Ti-oxide, Ni-oxide, W-oxide, Cu-oxide and so... Agent: Watchstone P+d, PLC

20080211541 - Precision voltage level shifter based on thin gate oxide transistors: A precision voltage level shifter based on thin gate oxide transistors is disclosed. A method of a voltage level shifter includes serially connecting thin n-channel gate oxide semiconductor FETs to think n-channel gate oxide semiconductor FETs to enable the voltage level shifter with a low input voltage. The method further... Agent: Texas Instruments Incorporated

20080211542 - Input buffer with wide input voltage range: The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.... Agent: Harness, Dickey & Pierce, P.L.C

20080211543 - 4-level logic decoder: The present invention relates to a 4-level logic decoder for decoding n 4-level input data signals into n 2-bit signals. The 4-level logic decoder comprises n decoding circuits with each decoding circuit comprising comparison circuitries for comparing the 4-level input data signal with a clock signal and a one-bit data... Agent: Nxp, B.v. Nxp Intellectual Property Department