Electronic digital logic circuitry inventions 08/08

20080204069 - Electronic module with organic logic circuit elements: The invention relates to an electronic module having two or more organic circuit elements connected together to give a logic circuit, said organic circuit elements being made up of organic components, in particular organic field effect transistors. The logic circuit comprises at least one filter module (5), which has an... Agent: Carella, Byrne, Bain, Gilfillan, Cecchi, Stewart & Olstein

20080204070 - Reduced power output buffer: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads... Agent: Van Pelt, Yi & James LLP

20080204071 - On-die termination circuit, method of controlling the same, and odt synchronous buffer: An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may... Agent: Harness, Dickey & Pierce, P.L.C

20080204072 - Programmable logic device: The invention relates to a connector (10) for connecting welding torch where the connector comprises a connector body (12) made of electrically insulating material, a cylindrical current transferring body (30) fitted on the cylindrical front part (13) of the connector body (12), made of electrically conductive material, where the current... Agent: Edwards Angell Palmer & Dodge LLP

20080204073 - Redundant configuration memory systems and methods: Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and at least one spare memory cell, wherein the at least one spare... Agent: Macpherson Kwok Chen & Heid LLP

20080204074 - Dedicated interface architecture for a hybrid integrated circuit: An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.... Agent: Lewis And Roca LLP

20080204076 - Integrated circuit and a method for designing a boundary scan super-cell: A method for designing an integrated circuit, the method includes: providing an initial definition of a boundary scan register that includes identical super-cells adapted to be connected to multiple pin types; and determining the configuration of each super-cell by providing at least one pin type indication signal to each super-cell.... Agent: Freescale Semiconductor, Inc. Law Department

20080204075 - Interfacing of circuits in an integrated electronic circuit: An interface having internal conductors to transfer data between a sending circuit and a receiving circuit in an integrated electronic circuit, the receiving circuit including an input buffer capable of receiving data and an output terminal for sending to the sending circuit an item of extraction information on each extraction... Agent: Seed Intellectual Property Law Group PLLC

20080204077 - Level shifter: A level shifter for shifting an input signal to an output signal. The level shifter includes an input buffer biased a first voltage and a ground voltage; an output buffer and a level-processing unit both biased between a second voltage and the ground voltage; and a voltage-drop unit coupled to... Agent: Kirton And Mcconkie

20080204078 - Level shifter for preventing static current and performing high-speed level shifting: A level shifter amplifies a voltage of a digital signal to a predetermined voltage and outputs the amplified signal. The level shifter is capable of preventing generation of static current, and performing high-speed level shifting by increasing the speed of charging electric charges into or discharging electric charges from an... Agent: Marger Johnson & Mccollom, P.C.

20080204079 - Level shifting circuits for generating output signals having similar duty cycle ratios: A level shifting circuit includes a level shifting unit and an output buffer unit. The level shifting unit generates first and second output signals responsive to first and second input signals. The first and second input signals range between first and second voltage levels, and the first and second input... Agent: Myers Bigel Sibley & Sajovec

20080204080 - Mobile circuit robust against input voltage change: An inverting flip-flop (F/F) circuit type monostable-bistable transition logic element (MOBILE) circuit that uses resonant tunneling diodes (RTDs) and can prevent a malfunction caused by low peak-to-valley current ratio (PVCR) characteristics of the RTD includes an input data conversion circuit and an inverting F/F circuit. The input data conversion circuit... Agent: Mills & Onello LLP

20080204081 - Clock gated circuit: A clock gated circuit includes a clock signal receiving unit that applies a first voltage to a fighting node when the clock signal is at a first logic; a discharging unit that discharges an electric charge from the fighting node when the clock signal is transitioned from the first logic... Agent: Mills & Onello LLP

20080204082 - Apparatus and method for generating a constant logical value in an integrated circuit: An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2n possible output combinations, where the n outputs assume a state that is a subset of the 2n possible output combinations and a second logic network... Agent: Kathy Manke Avago Technologies Limited

20080197875 - Integrated circuit: An integrated circuit is provided having at least one terminal for coupling and/or decoupling of electric signals, particularly of digital signals, and having integrated reference potential means, assigned to the terminal, for providing an electric reference potential to the terminal. It is provided according to an embodiment of the invention... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080197876 - Integrated circuit, system and method including a performance test mode: An integrated circuit includes N configurable cells each including one functional input, one output, one propagation input and one output. The circuit includes a functional mode in which the N configurable cells are coupled by their functional input and their output to logic blocks with which they cooperate to form... Agent: Graybeal, Jackson, Haley LLP

20080197877 - Per byte lane dynamic on-die termination: Embodiments of the invention are generally directed to systems, methods, and apparatuses for per byte lane dynamic on-die termination. In some embodiments, an integrated circuit includes logic to independently program at least one on-die termination (ODT) value for each of a plurality of integrated circuits coupled together through an interconnect.... Agent: Intel Corporation C/o Intellevate, LLC

20080197878 - Enhanced field programmable gate array: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.... Agent: Lewis And Roca LLP

20080197879 - Apparatus and method for a programmable logic device having improved look up tables: A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2N tri-state buffers coupled... Agent: Weaver Austin Villeneuve & Sampson LLP Attn: Altera

20080197881 - Receiver circuit using nanotube-based switches and logic: Receiver circuits using nanotube based switches and logic. Preferably, the circuits are dual-rail (differential). A receiver circuit includes a differential input having a first and second input link, and a differential output having a first and second output link. First, second, third and fourth switching elements each have an input... Agent: Wilmerhale/boston

20080197880 - Source driver and level shifting method thereof: The present invention provides a source driver comprising a shift register, a line buffer for storing a data signal and outputting a buffered data signal, and a level shifter for generating a level-shifted data signal based on the buffered data signal. The line buffer further comprises a charge pump supplying... Agent: Lowe Hauptman Ham & Berner, LLP

20080197882 - Logic circuits: A logic circuit includes a logic unit, a driving unit, and a voltage level adjuster. The logic unit includes an output node having a logic state, the logic unit being coupled to a first voltage reference. The driving unit includes an input node, the driving unit being coupled to a... Agent: Fish & Richardson PC

20080197883 - Integrated circuit device and electronic instrument: An integrated circuit device includes a first predriver that drives an N-type power MOS transistor of an external driver including the N-type power MOS transistor and a P-type power MOS transistor, a second predriver that drives the P-type power MOS transistor, a low-potential-side power supply pad, a first output pad,... Agent: Oliff & Berridge, PLC

20080197884 - Kick gate: Feedback is reduced by routing an input signal through a kick gate that opens for a predetermined time period then closes. The gate may be kept closed for a predetermined minimum time period before being allowed to open again. The gate is triggered open based on the input signal and... Agent: Fish & Richardson PC

20080191733 - Configurable ic with trace buffer and/or logic analyzer functionality: Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits for configurably performing different operations and several user design state (UDS) circuits for storing user-design state values. The IC further includes a trace buffer for storing user-design state values associated with an operational trigger... Agent: Adeli & Tollen, LLP

20080191734 - Semiconductor device including on-die termination control circuit having pipe line varying with frequency range: A semiconductor device according to example embodiments that may include an on-die termination (ODT) control circuit having a pipe line structure which changes in response to a frequency of a clock signal and a termination resistance generator for generating termination resistance in response to a termination resistance control signal.... Agent: Harness, Dickey & Pierce, P.L.C

20080191735 - Accessing multiple user states concurrently in a configurable ic: Some embodiments of the invention provide a configuration/debug network for configuring and debugging a configurable integrated circuit (IC). The configurable IC in some embodiments includes configurable resources (e.g., configurable logic resources, routing resources, memory resources, etc.) that can be grouped in conceptual configurable tiles that are arranged in several rows... Agent: Adeli & Tollen, LLP

20080191736 - Configurable ic with packet switch network: Some embodiments of the invention provide configurable integrated circuit (IC) that includes several configurable circuits that are conceptually in tiles. The IC also includes a first data network for passing data between the configurable circuits. The IC further includes a second packet-switch network for receiving packets of data from the... Agent: Adeli & Tollen, LLP

20080191737 - Reconfigurable sequencer structure: A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory... Agent: Kenyon & Kenyon LLP

20080191738 - Three dimensional integrated circuits: A three-dimensional semiconductor device, comprising: a programmable logic circuit; and a configuration circuit comprising a non planar memory element, wherein: a portion of the memory element is positioned above or below the logic circuit; and an output of the memory element is coupled to the logic circuit to program the... Agent: Raminda U. Madurawe

20080191739 - Method and apparatus for universal program controlled bus architecture: An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080191740 - Clock tree network in a field programmable gate array: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array... Agent: Lewis And Roca LLP

20080191741 - Integrated circuit having configurable cells and a secured test mode: An electronic circuit includes a plurality of configurable cells configured by a control circuit such as a test access controller when it receives a mode command signal: either in a functional state in which the configurable cells are functionally linked to logic cells with which they co-operate to form at... Agent: Hogan & Hartson LLP

20080191742 - Receiver circuit using nanotube-based switches and transistors: Receiver circuits using nanotube-based switches and transistors. A receiver circuit includes a differential input having a first and second input link, a differential output having a first and second output link, and first and second switching elements in electrical communication with the input links and the output links. Each switching... Agent: Wilmerhale/boston

20080191743 - Level shifter: Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage... Agent: Mcdermott Will & Emery LLP

20080191744 - Programmable current generator, current generation method and transmitter arrangement: A programmable current generator includes a decoder unit to generate a first and a second set of control signals as a function of a current control word. The current generator further includes a first and a second array of current sources, wherein the current sources of the first array generate... Agent: Eschweiler & Associates Llc

20080191745 - High-speed differential receiver: A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080186049 - Process and circuit for improving the life duration of field-effect transistors: The invention concerns a process and a circuit designed to improve the life duration of electronic field-effect integrated circuit transistors and in particular those with a thin film gate dielectric. According to the invention, an aging measurement tS is supplied by measuring the charge or discharge time at a reference... Agent: Lowe Hauptman & Berner, LLP

20080186050 - Impedance matching circuit, input-output circuit and semiconductor test apparatus: A characteristic test of a DUT having a low transmission line driving capability can be performed with a simple configuration and low cost. An impedance matching circuit is connected between a transmission line and a DUT in an input-output circuit of a semiconductor test apparatus. The impedance matching circuit includes:... Agent: Yasuo Muramatsu Muramatsu & Associates

20080186051 - Flexible multimode logic element for use in a configurable mixed-logic signal distribution path: A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The... Agent: Downs Rachlin Martin PLLC

20080186055 - Configuration setting circuit and configuration setting method thereof: The present invention provides a configuration setting circuit and the method thereof, in which the configuration setting circuit includes a clock generator, a plurality of terminals, and a frequency detector coupled to a terminal. The clock generator is used to generate multiple clock signals with different frequencies, and output through... Agent: Apex Juris, PLLC

20080186054 - Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path: A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, a design structure for a exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode,... Agent: Downs Rachlin Martin PLLC

20080186053 - Die apparatus having configurable input/output and control method thereof: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.... Agent: Christie, Parker & Hale, LLP

20080186052 - Methods, systems, and computer program products for using direct memory access to initialize a programmable logic device: Methods, systems, and computer program products for using direct memory access (DMA) to initialize a programmable logic device (PLD) are provided. A method includes manipulating a control line of the PLD to configure the PLD in a programming mode, receiving PLD programming data from a DMA control at a DMA... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080186056 - Programmable high-speed interface: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and... Agent: Townsend And Townsend And Crew LLP/ 015114

20080186057 - Low frequency detector including common input voltage sensor: A low frequency detector circuit includes a differential input that is received by an offset comparator circuit. The offset comparator circuit provides respective output signals COMPX and COMPY which can be compared to a generated threshold voltage Vcomp by an E2C (ECL to CMOS) comparators. The outputs of the E2C... Agent: Texas Instruments Incorporated

20080186058 - Level shifter for gate driver: A level shifter for a gate driver has a driving transistor, a reset transistor, a charge/discharge circuit, a threshold voltage detector, and a memory capacitor. An initial threshold voltage of the driving transistor is detected by the threshold voltage detector, and then memorized in the memory capacitor. The charge/discharge circuit... Agent: Jianq Chyun Intellectual Property Office

20080186059 - Semiconductor integrated circuit: The object of the present invention is to provide a semiconductor integrated circuit which enables reduction in clock skew between cell blocks, while having plural cell blocks in which standard cells with different cell heights are arranged. The semiconductor integrated circuit of the present invention includes a first standard cell... Agent: Greenblum & Bernstein, P.L.C