Electronic digital logic circuitry inventions 06/08

20080150574 - Method to reduce power in active shield circuits that use complementary traces: The present invention provides a method and apparatus for securing an integrated circuit. A pair of conductive security traces are arranged on an integrated circuit. Driver means provide complementary HIGH and LOW voltage levels to a respective first end of each of the conductive security traces. A first switch means... Agent: Schneck & Schneck

20080150575 - Latch-up prevention circuitry for integrated circuits with transistor body biasing: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute... Agent: G. Victor Treyz

20080150576 - Register device and methods for using such: Various systems and methods for registering data are disclosed herein. For example, some embodiments of the present invention provide test enabled flip-flop devices. Such devices include a test mode input signal and a register output signal. In addition, the devices include a flip-flop with a data input and a clock... Agent: Texas Instruments Incorporated

20080150577 - Interface circuit: An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20080150579 - Alterable application specific integrated circuit (asic): A semiconductor device includes a plurality of circuit blocks; and a configuration circuit coupled to the plurality of circuit blocks to program the circuit blocks, the configuration circuit comprising a plurality of memory elements, the memory elements further comprising: a first set of memory elements to store a first instruction;... Agent: Raminda U. Madurawe

20080150578 - Dynamically configurable logic gate using a non-linear element: Dynamically Configurable Logic Gate Using a Nonlinear Element A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20080150580 - Three input field programmable gate array logic circuit configurable as a three input look up table, a d-latch or a d flip- flop: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the... Agent: Lewis And Roca, LLP

20080150581 - Bidirectional signal interface and related system and method: An embodiment of a bidirectional signal interface includes first and second nodes and first and second translating circuits. The first and second nodes are respectively operable to receive a first logic signal and a second logic signal. The first translating circuit has a first signal path coupled between the first... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20080150582 - Semiconductor memory device for internally controlling strength of output driver: Provided is a semiconductor memory device that is capable of internally controlling a strength of an output driver. The semiconductor memory device includes: an OCD (off chip driver) control signal generator for decoding EMRS and addresses to generate a plurality of external strength control signals or an internal driving signal;... Agent: Mcdermott Will & Emery LLP

20080150583 - Buffer circuit: A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a... Agent: Akin Gump LLP - Silicon Valley

20080150584 - Cml circuit: Disclosed herein is a CML circuit that can solve a conventional problem that it has been impossible to input a large amplitude signal to a differential pair. The CML circuit of the present invention includes an internal signal generation circuit for generating an input differential signal having an amplitude to... Agent: Sughrue Mion, Pllc

20080150585 - Impedance control for signal interface of a network node: The terminating impedance of a networked device in a wired communication channel is controlled to avoid an impedance discontinuity when power is applied and removed from the node or other event occurs that would change the impedance of the signal interface. When the node transmits or receives signals using the... Agent: Townsend And Townsend And Crew, LLP

20080150586 - Semiconductor device, method of manufacturing same, and apparatus for designing same: A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080150587 - Clocked inverter, nand, nor and shift register: A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a... Agent: Eric Robinson

20080143373 - Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080143374 - Anti-see protection techniques for high-speed ics with a current-switching architecture: Protection against anti single event effects associated with strikes of energetic particles is provided in current-mode logic (CML) or similar integrated circuits (ICs) using a current-switching architecture.... Agent: Schiff Hardin, LLP Patent Department

20080143376 - Leakage efficient anti-glitch filter: A leakage efficient anti-glitch filter. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter with variable delay stages comprises a plurality of variable delay stages and a coincidence detector element for detecting coincidence of an input signal to the delay element and an output... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20080143375 - Method for reducing cross-talk induced source synchronous bus clock jitter: A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.c.

20080143377 - Impedance calibration circuit and semiconductor device including the same: An impedance calibration circuit and a semiconductor device including the same are provided. An embodiment of the invention provides an impedance calibration circuit with a variable reference voltage generation unit. The impedance calibration circuit maximizes the number of semiconductor devices that can be tested in test equipment at one time... Agent: Volentine & Whitt Pllc

20080143378 - Apparatus and methods for communicating with programmable logic devices: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device... Agent: Townsend And Townsend And Crew LLP/ 015114

20080143380 - Low static current drain logic circuit: A logic circuit is disclosed that is tolerant of logic signals with voltages different from the voltage of the logic circuit power supply. In one embodiment, the logic circuit has an inverting amplifier therein, the amplifier having at least one input and an output and is powered by the power... Agent: Mendelsohn And Associates, P.c.

20080143379 - Reprogrammable circuit board with alignment-insensitive support for multiple component contact types: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to... Agent: Mcdermid, Turnbull & Anglehart Patent And Trade-mark Agents

20080143381 - Functional cells for automated i/o timing characterization of an integrated circuit: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions... Agent: Texas Instruments Incorporated

20080143382 - Programming matrix: The invention relates to a programming matrix for the switching of one of n logical inputs to one of j outputs, whereby the programming matrix comprises a slot system with magnetic elements in selected positions, the magnetic and/or electrical properties of which can change or be changed.... Agent: Young & Thompson

20080143383 - Using a delay clock to optimize the timing margin of sequential logic: A circuit including a first stage register that operates in response to a first clock having a period TCYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational... Agent: Bever, Hoffman & Harms, LLP

20080143385 - High-speed differential logic to cmos translator architecture with low data-dependent jitter and duty cycle distortion: Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals.... Agent: Brownstein Hyatt Farber Schreck, Pc

20080143384 - Printed circuit unit based on organic transistor: A printed circuit unit implementing with organic transistors is provided. The printed circuit unit includes an input signal circuit, a load circuit and a level shifter. The input signal circuit includes N serially connected organic transistors. When one of the serially connected organic transistors is cut-off, the signal input circuit... Agent: Jianq Chyun Intellectual Property Office

20080143386 - Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive... Agent: Slater & Matsil LLP

20080143387 - Software programmable multiple function integrated circuit module: An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable function circuits are either interconnected to each other or connected to a plurality of output... Agent: Mou-shiung Lin

20080143388 - Parallel bipolar logic devices and methods for using such: Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transistors in each of the differential pairs are all electrically coupled... Agent: Texas Instruments Incorporated

20080143389 - Logic circuits using carbon nanotube transistors: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.... Agent: Intel/blakely

20080136441 - Semiconductor integrated circuit and measuring method of terminator resistor in the semiconductor integrated circuit: A semiconductor integrated circuit for receiving a signal having been propagated through a transmission line, has a control circuit that controls on/off of a first to fourth switching circuits, wherein the control circuit turns off the first switching circuit and the second switching circuit and turns on the third switching... Agent: Amin, Turocy & Calvin, LLP

20080136442 - Signal isolator using micro-transformers: A logic signal isolator including a micro-transformer with a primary winding and a secondary winding. A transmitter circuit drives the primary winding in response to a received input logic signal such that, in response to a first type of edge in the logic signal, at least a first amplitude signal... Agent: Iandiorio & Teska

20080136444 - Device for a line termination of two-wire lines: A device for a line termination of two-wire lines having at least one first and second terminating resistant between the two wires is provided, the first and the second terminating resistors being connected in series, and at least one switching arrangement being provided between the two terminating resistors.... Agent: Kenyon & Kenyon LLP

20080136443 - Input termination for delay locked loop feedback with impedance matching: A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the... Agent: Bever, Hoffman & Harms, LLP

20080136445 - Synchronous elastic designs with early evaluation: Embodiments of early enabling synchronous elastic designs, devices and methods are presented herein.... Agent: Lee & Hayes, Pllc

20080136446 - Block level routing architecture in a field programmable gate array: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of the B16×16 tile, and also associated with each... Agent: Sierra Patent Group, Ltd.

20080136447 - Method and apparatus for implementing complex logic within a memory array: A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080136448 - State machine and system and method of implementing a state machine: A system and method for implementing a state machine including a plurality of states, the state machine configured to transition from a present state to a next state in response to input. One embodiment of the system includes a plurality of state elements, each of the plurality of state elements... Agent: Ostrolenk Faber Gerb & Soffen

20080136449 - Dedicated crossbar and barrel shifter block on programmable logic resources: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality... Agent: Ropes & Gray LLP

20080136450 - Maintaining input and/or output configuration and data state during and when coming out of a low power mode: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing... Agent: Baker Botts L.l.p. One Shell Plaza

20080136451 - Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing... Agent: Baker Botts L.l.p. One Shell Plaza

20080136453 - Digital temperature detecting system and method: A digital temperature detecting system for detecting a working temperature of a chip. The digital temperature detecting system includes a clock generator, for generating a first clock signal having a constant frequency; an oscillating circuit having a plurality of Not gates coupled in series, for generating a second clock signal,... Agent: Kirton And Mcconkie

20080136452 - True/complement generator having relaxed setup time via self-resetting circuitry: An integrated circuit includes a data node, an output node, and set logic coupling to the data node to the output node. The set logic changes a state of the output node in response to a change in state of the data node. The integrated circuit also includes a reset... Agent: Dillon & Yudell LLP

20080136454 - Ballistic deflection transistor and logic circuits based on same: A quantum well is formed in a substrate to define a hub, ports extending from the hub, and a deflective structure in the hub. Electrons move through the hub and ports according to the ballistic electron effect. Gates control the movement of the electrons, causing them to be incident on... Agent: Blank Rome LLP

20080136455 - Electronic device and method and performing logic functions: An electronic device is presented which is configured to operate as at least one logic gate. The device comprises an electrodes arrangement of one or more basic units, the basic unit being configured to define at least one vacuum space for free charged particles' propagation and comprising an input assembly... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080129328 - Quasi-particle interferometry for logical gates: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for ν= 5/2's FQHE (Nucl. Phys. B 360, 362 (1991))... Agent: Woodcock Washburn LLP (microsoft Corporation)

20080129329 - Method of testing connectivity using dual operational mode cml latch: A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at least one clock signal and... Agent: International Business Machines Corporation Dept. 18g

20080129330 - Integrated circuit having state-saving input-output circuitry and a method of testing such an integrated circuit: An integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged between the output of a plurality of respective I/O receivers and the internal digital, analog, or... Agent: Downs Rachlin Martin Pllc

20080129331 - System for transmission line termination by signal cancellation: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080129332 - On-chip source termination in communication systems: A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision resistor, such as an unsilicided poly resistor, or any other suitable termination. As compared to an off-chip source termination, the on-chip source termination can reduce voltage peaking and/or... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080129333 - Configurable integrated circuit with built-in turns: Some embodiments of the invention provide configurable integrated circuits (“IC's”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects... Agent: Adeli & Tollen, LLP

20080129334 - Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes: Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on... Agent: Peter Su

20080129335 - Configurable ic with interconnect circuits that have select lines driven by user signals: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes a first set of circuits and a second set of circuits interspersed among the first set of circuits. Each set of circuits includes at least ten volatile configurable circuits. Several circuits in at least one of... Agent: Adeli & Tollen, LLP

20080129336 - Via programmable gate array with offset direct connections: Some embodiments of the invention provide configurable via programmable gate array (“VPGA”) with several configurable circuits arranged in a configurable circuit arrangement. In some embodiments, the configurable circuit arrangement is a configurable circuit arrangement that includes numerous (e.g., 50, 100, etc.) configurable circuits that are arranged in several rows and... Agent: Adeli & Tollen, LLP

20080129337 - Method and apparatus for performing shifting in an integrated circuit: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic... Agent: Adeli & Tollen, LLP

20080129338 - High-speed asynchronous digital signal level conversion circuit: Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at which the input signal of the... Agent: Rabin & Berdo, Pc

20080129339 - Level shift circuit with voltage pulling: A level shift circuit with voltage pulling includes a voltage-pulling circuit and at least one inverter. The voltage-pulling circuit contains a capacitance element, a first switch receiving a first voltage and charging the capacitance element according to a first control signal, a second switch discharging the capacitance element and being... Agent: Wpat, Pc Intellectual Property Attorneys

20080129340 - Logic circuits with electric field relaxation transistors and semiconductor devices having the same: In a logic circuit, a first switching device is connected between a first voltage and an output terminal through which an output signal is output. The switching device is selectively activated and deactivated based on an input signal. A second switching device is connected to a ground voltage and is... Agent: Harness, Dickey & Pierce, P.L.C

20080129341 - Semiconductor apparatus: A semiconductor apparatus that is effective for problems of local characteristic variations and that enables higher speed and lower power consumption. Semiconductor apparatus 100 has: a plurality of sensor circuits 101a to 101g which are arranged evenly inside semiconductor apparatus 100 and detect local characteristic variations at their respective positions... Agent: Greenblum & Bernstein, P.L.C

20080129342 - Configurable delay chain with stacked inverter delay elements: A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a... Agent: Murabito, Hao & Barnes LLP