Electronic digital logic circuitry inventions 05/08

20080122478 - Output slew rate control: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter... Agent: Schwegman, Lundberg & Woessner, P.A.

20080122479 - Low power consumption mis semiconductor device: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation... Agent: Buchanan, Ingersoll & Rooney PC

20080122480 - Method for setting up a serial communication port configuration: A method for setting up a serial communication port configuration is disclosed. The method comprises a hardware circuit of a motherboard having a plurality of digital logic gates and a plurality of chips disposed thereon, wherein a process is initiated when the digital logic gates receive a high or low... Agent: Evalue Technology Inc.

20080122481 - Programmable system on a chip: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic... Agent: Sierra Patent Group, Ltd.

20080122482 - Data processing system: The present invention provides an architecture code 20 including object circuit information 23 for mapping an object circuit that is at least part of a circuit for executing an application onto part of a logic circuit where circuits can be dynamically reconfigured, interface circuit information 24 for mapping an interface... Agent: Marshall, Gerstein & Borun LLP

20080122484 - Integrated circuit device having state-saving and intitalization feature: An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A control circuit such as a state machine controls the saving of... Agent: Sierra Patent Group, Ltd.

20080122483 - Low power mode: An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During... Agent: Silicon Valley Patent Group LLP Attn: Bryan H. Wyman

20080122485 - Semiconductor device: A semiconductor device includes an external pin, a control parameter decision circuit, and a register update circuit. The control parameter decision circuit includes a register and an output selector. The register is initialized in accordance with resetting of the semiconductor device. The output selector, according to a level value of... Agent: Arent Fox LLP

20080122486 - Circuit and methodology for high-speed, low-power level shifting: A level shifting circuit and methodology involving a switching current generator responsive to switching of an input signal for producing a switching current to switch an output signal, and a holding current generator for producing a holding current to hold the logic level of the output signal in accordance with... Agent: Mcdermott Will & Emery LLP

20080122487 - Low power logic output buffer: A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes first, second, third... Agent: Panitch Schwarze Belisario & Nadel LLP

20080122488 - Output driving circuit: Disclosed is an output driver, which comprises: a resistance element with resistance, coupled to an output terminal; a current mode driving circuit, coupled to the resistance element, for providing a first current to the output terminal, wherein at least one of the amount of the first current and the resistance... Agent: North America Intellectual Property Corporation

20080122489 - Communication interface employing a differential circuit and method of use: A communication interface employing a differential circuit and method of use is disclosed. In one form, a circuit operable to communicate signals via a communication bus can include a differential signaling circuit operable to be coupled to a communication bus. The differential signaling circuit can include a first current carrying... Agent: Larson Newman Abel Polansky & White, LLP

20080116929 - Register circuit, scanning register circuit utilizing register circuits and scanning method thereof: The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled to a non-test data and a test data respectively, for selectively outputting the non-test data or the test data as... Agent: North America Intellectual Property Corporation

20080116930 - Hybrid high-speed/low-speed output latch in 10 gbps interface with half rate clock: A high-speed serial demultiplexer receives over four high-speed serial data lines at a nominal rate of 10 GBPS and demultiplexes the data to 16 lines with a rate of 2.5 GHz each. The demultiplexer circuits are configured as two D type latches, one of which latches data on the positive... Agent: Garlick Harrison & Markison

20080116931 - Embedding memory within tile arrangement of a configurable ic: Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably... Agent: Adeli & Tollen, LLP

20080116932 - Structured asic layout architecture having tunnel wires: The present invention discloses a structured ASIC layout architecture, which includes a fixed body region and a programmable layout region. The fixed body region includes a tunnel wire or multiple tunnel wires for providing a function capability or multiple function capability. The programmable layout region is disposed on the fixed... Agent: J C Patents, Inc.

20080116933 - Integrated circuit device and electronic instrument: An integrated circuit device includes data pads, I/O circuits, each of the I/O circuits respectively receiving a CMOS level data signal from one of the data pads, a high-speed I/F circuit block that includes a physical layer circuit and transfers data through a serial bus using differential signals, and a... Agent: Oliff & Berridge, Plc

20080116934 - Semiconductor integrated circuit device: A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080116936 - Differential bidirectional transceiver and receiver therein: A differential bidirectional transceiver is provided. The differential bidirectional transceiver includes a first current transmitter, a second current transmitter and a receiver. The first current transmitter and the second current transmitter are coupled to a first interconnection and a second interconnection, respectively. Each of the current transmitters includes two current... Agent: Jianq Chyun Intellectual Property Office

20080116935 - Source-coupled differential low-swing driver circuits: A novel source-coupled differential driver circuit fully compatible with digital visual interface TMDS signaling specification is disclosed. Driven output signals are connected to the source terminals of driving switches in the invention circuit, minimizing the detrimental impact of miller coupling capacitance between gate nodes and driven output nodes upon output... Agent: Rajendran Nair Comlsi Inc.

20080116937 - Semiconductor integrated circuit: A semiconductor integrated circuit including: a data input circuit inputting a data input signal from outside and outputting the signal; a comparison value register memorizing an expectation value of the output signal varying in accordance with an input to the data input circuit; and a comparing circuit comparing a value... Agent: Arent Fox LLP

20080116938 - Hybrid keeper circuit for dynamic logic: A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.c.

20080116939 - Semiconductor device, logic circuit and electronic equipment: A semiconductor device comprises: a) a multiple layered substrate including a semiconductor substrate, an insulation film formed on the semiconductor substrate, and a semiconductor film, b) a first inverter having a first n-channel type MISFET and a first p-channel type MISFET connected in series each other, being formed on a... Agent: Oliff & Berridge, Plc

20080111579 - Anti-tamper electronic obscurity using e-fuse technology: A design structure embodied in a machine readable medium used in a design process includes a circuit that employs an anti-tamper sensor. The circuit employs an anti-tamper sensor that includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples... Agent: Ibm Corporation

20080111580 - Suppressing ringing in high speed cmos output buffers driving transmission line load: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating... Agent: Docket Clerk

20080111581 - Configurable asic for use with a programmable i/o module: An application-specific integrated circuit (ASIC) for use with a programmable I/O module includes programmable circuitry that enables the ASIC to be configured to support various different I/O functions. The ASIC includes a pin interface, a data interface, a digital section, and an analog section. The pin interface supports analog and... Agent: Kathy Manke Avago Technologies Limited

20080111584 - Longitudinal balance calibration for a subscriber line interface circuit: A method of calibrating longitudinal balance for a subscriber line interface circuit includes providing a first and a second driver of a differential driver pair for driving a subscriber line. An output of each of the first and second drivers is coupled to a common output. The common output is... Agent: Davis & Associates

20080111582 - Memory module and memory device: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal,... Agent: Young & Thompson

20080111583 - Implementing logic functions with non-magnitude based physical phenomena: An n-valued switch with n≧2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances... Agent: Diehl Servilla Llc

20080106297 - Slew rate controlled circuits: A slew rate controlled output buffer. The slew rate controlled output buffer comprises a pre-driver circuit having a data input node and a data output node and a driver circuit coupled to the output node of the pre-driver circuit. The pre-driver circuit comprises a plurality of inverters connected in parallel,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080106301 - Semiconductor integrated circuit capable of autonomously adjusting output impedance: A semiconductor integrated circuit includes an output driver, a replica driver, a replica resistor, and an impedance adjustment circuit. The output driver is configured to be capable of changing current driving capability. The replica driver is configured to be capable of changing current driving capability. The replica resistor is connected... Agent: Young & Thompson

20080106302 - Domino circuit with disable feature: Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.... Agent: Intel/blakely

20080106298 - Mos linear region impedance curvature correction: A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS... Agent: Jones Day

20080106299 - Semiconductor integrated circuit having current leakage reduction scheme: A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080106300 - Method and apparatus for programmably powering down structured application-specific integrated circuits: Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.... Agent: Ropes & Gray LLP

20080106303 - Multiple-output transistor logic circuit: A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate... Agent: Martin D. Moynihan

20080100335 - Apparatus and method for determining on die termination modes in memory device: For determining an on die termination (ODT) mode in a semiconductor memory device, a first mode determining unit determines whether or not a normal ODT mode is enabled from performing a logic operation on a first set of signals. A second mode determining unit determines whether or not a dynamic... Agent: Law Office Of Monica H Choi

20080100334 - Impedance matching circuit and semiconductor memory device with the same: An impedance matching circuit performs a ZQ calibration for a test on a wafer process of a semiconductor memory device. The impedance matching circuit of the semiconductor memory device includes a first pull-down resistance unit, a first pull-up resistance unit, a second pull-up resistance unit and a second pull-down resistance... Agent: Mcdermott Will & Emery LLP

20080100333 - Impedance matching circuit of semiconductor memory device: An impedance matching circuit reduces current consumption during ZQ calibration in the present invention. The impedance matching circuit includes a reference voltage generator, a code generator, a first pull-up resistance unit, a second pull-up resistance unit and a pull-down resistance unit. The reference voltage generator generates a reference voltage. The... Agent: Mcdermott Will & Emery LLP

20080100337 - Memory circuit, semiconductor device and read control method of memory circuit: A memory circuit of the invention comprises N look-up tables for implementing a desired logic function of L inputs/M outputs by partitioning a memory cell array including a plurality of memory cells into portions each corresponding to at least a predetermined number of input/output paths; a decode circuit for selecting... Agent: Mcginn Intellectual Property Law Group, PLLC

20080100340 - Low voltage complementary metal oxide semiconductor process tri-state buffer: A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first... Agent: Rabin & Berdo, PC

20080100341 - Level shifter having single voltage source: Embodiments relate to a level shifter which uses a single voltage source, has an excellent operation characteristic even when a difference between a low voltage and a high voltage is large, and can be easily designed. Embodiments relate to a level shifter for shifting a voltage level between an input... Agent: Sherr & Nourse, PLLC

20080100342 - Circuit arrangement comprising a level shifter and method: A circuit arrangement includes a first level shifter, an output stage, and a feedback circuit. The first level shifter is coupled to receive an input signal having a first voltage level from an input terminal, and is configured to provide a level-shifted signal having a second voltage level higher than... Agent: Maginot, Moore & Beck Chase Tower

20080100343 - Source driver and level shifting apparatus thereof: The present invention discloses a source driver and a level shifting apparatus thereof. The level shifting apparatus comprises a level shifter and an asynchronous dynamic control circuit. The level shifter has a first switch and connected to a high power supply voltage source via the first switch, wherein the level... Agent: Lowe Hauptman Ham & Berner, LLP

20080100344 - Scannable dynamic logic latch circuit: A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20080100336 - Hybrid logic/interconnect circuit in a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic... Agent: Adeli & Tollen, LLP

20080100338 - Logic circuit apparatus: A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080100339 - Configurable ic with routing circuits with offset connections: Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a... Agent: Adeli & Tollen, LLP

20080100345 - Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays: Various method and system embodiments of the present invention are directed to implementing serial logic gates using nanowire-crossbar arrays with spintronic devices located at nanowire-crossbar junctions. In one embodiment of the present invention, a nanowire-crossbar array comprises a first nanowire and a number of substantially parallel control nanowires positioned so... Agent: Hewlett Packard Company