Electronic digital logic circuitry inventions 04/08

20080094099 - Differential line compensation apparatus, method and system: A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition... Agent: Slater & Matsil LLP

20080094102 - Reprogrammable instruction dsp: A software programmable DSP with a field programmable instruction set is described where customized instructions can be created, or certain existing instructions can be modified, at the user's location after taking delivery of the processor. The FPGA fabric used to implement the reprogrammable instructions is restricted to supporting the software-programmable... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20080094103 - Programmable multiplexer: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer... Agent: Silicon Valley Patent Group LLP Attn: Bryan H. Wyman

20080094105 - Programmable multiple supply regions with switched pass gate level converters: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage... Agent: Martine Penilla & Gencarella, LLP

20080094106 - Apparatus for configuring i/o signal levels of interfacing logic circuits: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage... Agent: Hewlett Packard Company

20080094100 - Adjustable transistor body bias generation circuitry with latch-up prevention: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe... Agent: G. Victor Treyz

20080094101 - Programmable system on a chip for power-supply voltage and current monitoring and control: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring,... Agent: Sierra Patent Group, Ltd.

20080094104 - High speed double data rate jtag interface: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal... Agent: Texas Instruments Incorporated

20080088339 - Hard macro with configurable side input/output terminals, for a subsystem: A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time critical input data to be processed and at least one time critical output terminal (COT)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080088340 - Miller capacitance tolerant buffer element: A buffer includes a source follower module and a pull-up/pull-down module that is connected to the source follower module. An output signal at the output terminal of the source follower module follows an input signal at the input terminal with a predetermined delay, independent of the Miller capacitance. The pull-up/pull-down... Agent: Freescale Semiconductor, Inc. Law Department

20080088341 - Level shifter circuit: A level shifter circuit for ensuring a high impedance state even in a transitional period such as when activating an external power supply while reducing power consumption. A latch circuit is set to a low level by a set circuit when a high potential power supply voltage increases. When the... Agent: Freescale Semiconductor, Inc. Law Department

20080088338 - Semiconductor memory device for adjusting impedance of data output driver: A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the... Agent: Mcdermott Will & Emery LLP

20080088342 - Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications: A digital data transmitting device is disclosed having differential signaling circuitry, a current source controller and a pair of transistor-implemented current sources is disclosed. The current source controller generates a current source control signal based on a detected mode of operation of the differential signaling circuitry. The pair of transistor-implemented... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20080088343 - Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability: Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability, is provided and described. In one embodiment, switches are set to a first switch position to operate the repeater circuit in the high performance repeater mode. In another embodiment, switches... Agent: Murabito, Hao & Barnes LLP

20080088344 - Automatic extension of clock gating technique to fine-grained power gating: A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The... Agent: Macpherson Kwok Chen & Heid LLP

20080088345 - Quad state logic design methods, circuits, and systems: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.... Agent: Texas Instruments Incorporated

20080084231 - Method for implementing level shifter circuits and low power level shifter circuits for integrated circuits: A low power level shifter circuit for integrated circuits, and a design structure on which the subject circuit resides are provided. The low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080084230 - Interconnect structure enabling indirect routing in programmable logic: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080079457 - High speed io buffer: A bi-directional buffer is provided. The buffer includes a driver, a receiver, and a circuitry configured to select a driving mode in response to detecting a first condition and to select a receiving mode in response to detecting a second condition. The driving mode has a first impedance and the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080079459 - Integrated circuit and input data controlling method for reconfigurable circuit: An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a... Agent: Arent Fox LLP

20080079460 - Programmable logic cell, configurable cell, configurable cell arrangement, configurable logic array, mask programmable basic cell, mask programmable gate array and method: A mask programmable logic cell for configuration of at least one either LUT-based and MUX-based configurable cell comprises a first set of 2:1 multiplexers each having two input terminals and one select terminal and a second set of 4:1 multiplexers each having four input terminals and comprising three hierarchal arranged... Agent: Maginot, Moore & Beck Chase Tower

20080079461 - Integrated circuit chips with fine-line metal and over-passivation metal: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node... Agent: John Chen

20080079458 - Impedance-controlled pseudo-open drain output driver circuit and method for driving the same: An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a... Agent: Blakely Sokoloff Taylor & Zafman

20080079462 - Digital a/v transmission phy signaling format conversion, multiplexing, and de-multiplexing: A circuit includes a configurable receiver circuit, a multiplexer or demultiplexer coupled to the configurable receiver circuit, and a configurable driver circuit coupled to the multiplexer or demultiplexer. The configurable receiver circuit generates an internal format signal which is received by the multiplexer or demultiplexer. The configurable driver circuit receives... Agent: Fenwick & West LLP