Electronic digital logic circuitry inventions 03/08

20080068040 - Semiconductor device and impedance adjusting method thereof: There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing... Agent: Miles & Stockbridge PC

20080068043 - Low to high voltage conversion output driver: A low to high voltage conversion output driver. The low to high voltage conversion output driver has an output coupled to a first fixed voltage via a load device and comprises a current source, a low voltage transistor, and a high voltage transistor. The current source has one end coupled... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080068039 - Wafer level i/o test, repair and/or customization enabled by i/o layer: A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip... Agent: Whitham, Curtis, & Christofferson, P.C.

20080068041 - Look-up table structure with embedded carry logic: A configurable look up table (LUT) structure of an integrated circuit comprising: a first, a second and a third intermediate LUT stage, each of the LUT stages comprising one or more inputs and an output, wherein: the output of first intermediate LUT stage is coupled to an input of the... Agent: Raminda U. Madurawe

20080068042 - Programmable system in package: Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a... Agent: Adeli & Tollen, LLP

20080061816 - Production of limited lifetime devices achieved through e-fuses: An apparatus for disabling a circuit when the circuit is in a first preselected condition includes a critical element that has an enable state and a disable state. The critical element is configured in relation to the circuit such that the circuit cannot operate normally if the critical element is... Agent: Robert R. Williams IBM Corporation, Dept. 917

20080061818 - Techniques for providing calibrated on-chip termination impedance: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to... Agent: Steven J. Cahill

20080061825 - Cml to cmos signal converter: A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power... Agent: International Business Machines Corporation Dept. 18g

20080061826 - Signal history controlled slew-rate transmission method and bus interface transmitter: A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080061828 - Inductor-tuned buffer circuit with improved modeling and design: According to one exemplary embodiment, an inductor-tuned buffer circuit includes at least one input transistor for receiving a time varying input signal, where the at least one input transistor drives an output of the buffer circuit. The buffer circuit further includes a buffer inductor coupled to the output of the... Agent: Farjami & Farjami LLP

20080061830 - Method, apparatus, and system providing power supply independent imager output driver having a constant slew rate: An output driver having an output that is not dependant on the variation of the voltage level of a variable supply voltage. The output driver, having at least two power supply voltages and which is not influenced by the variation of the voltage level of a variable power supply, leads... Agent: Dickstein Shapiro LLP

20080061829 - Methods and apparatus for reducing duty cycle distortion in a multiple-stage inverter: An apparatus and method are disclosed which may include a multiple-stage inverter circuit, having at least first, second, and third stages, wherein a ratio (Rm-(m-1)) between a size of a given one of said stages “m” to a size of a stage “m-1” immediately preceding stage m is less than... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20080061832 - Protection circuits and methods of protecting circuits: A circuit configured for providing hot-carrier effect protection, the circuit comprising a first transistor including a first terminal and a second terminal, the first terminal being coupled to a conductive pad, a switch device including a terminal coupled to the conductive pad, and a control circuit configured for keeping the... Agent: Panitch Schwarze Belisario & Nadel LLP

20080061833 - Semiconductor device having a pseudo power supply wiring: A semiconductor device includes main power supply wirings VDD and VSS, an pseudo power supply wiring VDT, inverters connected between the pseudo power supply wiring VDT and the main power supply wiring VSS, and inverters connected between the main power supply wiring VDD and the main power supply wiring VSS.... Agent: Foley And Lardner LLP Suite 500

20080061831 - Slew rate controlled digital output buffer without resistors: An output buffer for an IC includes a PMOS transistor having a source coupled to an operating voltage, and an NMOS transistor serially coupled between a drain of the PMOS transistor and a complementary operating voltage. A first driver is coupled to a gate of the PMOS transistor for selectively... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080061835 - Synchronizing modules in an integrated circuit: A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first... Agent: Docket Clerk

20080061836 - Current mirror and parallel logic evaluation: Methods, apparatuses, and systems to improve performance of integrated circuits are discussed. Some embodiments comprise methods to increase rates of logic evaluation in integrated circuits. The methods generally involve evaluating logic in one or more logic branches, where one of more of those branches employs a current mirror, and outputting... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20080061817 - Changing chip function based on fuse states: Systems, methods, and design structures whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080061819 - Memory chip having a complex termination: A memory chip has a signal line and a complex impedance which is connected to the signal line for termination of the signal line. A memory having such a memory chip and a method for operating a memory chip are also described. The memory chip on the memory having a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080061820 - Mos linear region impedance curvature correction: A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS... Agent: Jones Day

20080061821 - Apparatus and methods for multi-gate silicon-on-insulator transistors: An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set gate bias of one gate of the one or more multi-gate transistors within... Agent: Law Offices Of Maximilian R. Peterson

20080061822 - Programmable system on a chip for power-supply voltage and current monitoring and control: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring,... Agent: Sierra Patent Group, Ltd.

20080061823 - Configurable ic's with logic resources with offset connections: Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic... Agent: Adeli & Tollen, LLP

20080061824 - Variable threshold transistor for the schottky fpga and multilevel storage cell flash arrays: An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays,... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080061827 - Floating driving circuit: A floating driving circuit according to the present invention comprises an input circuit to receive an input signal. A latch circuit receives a trigger signal for generating a latch signal. The latch signal is used to turn on/off a switch. A coupling capacitor is connected between the input circuit and... Agent: Rosenberg, Klein & Lee

20080061834 - Reconfigurable semiconductor intergrated circuit and processing assignment method for the same: A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line... Agent: Mcdermott Will & Emery LLP

20080061837 - Low supply voltage, large output swing, source-terminated output driver for high speed ac-coupled double-termination serial links: A current mode logic circuit includes a current mode logic driver circuit and a transistor biasing improvement circuit. The transistor biasing improvement circuit includes a first current source coupled to a first output node of the current mode logic driver circuit and a second current source coupled to a second... Agent: Thomas C. Chuang

20080054933 - Scan chain in a custom electronic circuit design: The present invention relates to a scan chain and related cell design structures in a custom electronic circuit design with a plurality of storage elements. All scan inputs and all scan outputs of the storage elements are propagated to a top level of the design hierarchy in design. Each scan... Agent: Ibm Microelectronics Intellectual Property Law

20080054935 - Method and apparatus for output driver calibration, and memory devices and system embodying same: A method, system, and output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calibrating p-channel devices in the output driver with the averaged pull-up count signal being an average... Agent: Trask Britt

20080054937 - Output circuit of semiconductor device: An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in... Agent: Mcginn Intellectual Property Law Group, PLLC

20080054936 - Output circuit of semiconductor device and semiconductor device including thereof: An output circuit includes a counter circuit that generates an ODT control signal ODTa, plural driver circuits having the ODT function, a synchronizing circuit that synchronizes a signal transmitted from the counter circuit to the driver circuit with an internal clock DLL, a first selecting circuit that activates one of... Agent: Foley And Lardner LLP Suite 500

20080054938 - Microcontroller with low noise peripheral: A microcontroller may have at least a first and second output port coupled with external first and second pins, respectively, a programmable switching arrangement operable in a first mode to provide for a first and second output signal at the first and second pins, respectively, and in a second mode... Agent: Baker Botts, LLP

20080054939 - Creating high-drive logic devices from standard gates with minimal use of custom masks: Logic cells in an application-specific integrated circuit (ASIC) emulating standard gate sizing by duplicating elements within a single standard gate where logical high-drive gates are synthesized and converted to parallel elements as a post-process. The drive characteristics of the logical gates are retained during the conversion to the physical gate... Agent: Tillman Wright, PLLC

20080054942 - Method and apparatus for generating a reference signal and generating a scaled output signal based on an input signal: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the... Agent: Advanced Micro Devices, Inc. C/o Vedder Price Kaufman & Kammholz, P.C.

20080054944 - Method and circuit for producing symmetrical output signals tolerant to input timing skew, output delay/slewrate-mismatch, and complementary device mismatch: An electronic circuit, including a signal transmitter, a signal generator and a ring oscillator, has a topography that is entirely symmetrical so that signals transmitted or produced by the circuit have symmetrical output signals tolerant to input timing skew, output delay/slewrate-mismatch, and complementary device-mismatch. Each P-type transistor in the circuit... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080054943 - Variable switching point circuit: A variable switching point inverter (30) is disclosed which lowers the threshold voltage lowered for both rising and falling edge input voltages (VIN) by changing the P/N ratio of the inverter based on the delayed output state (VOUT) of the inverter. The variable switching point inverter may be constructed as... Agent: Hamilton & Terrile, LLP

20080054945 - Method and apparatus for loss-of-clock detection: Methods and apparatus are provided for loss-of-clock detection. A loss of a clock signal is detected by delaying the clock signal using one or more delay elements; and applying an output of the one or more delay elements to at least one logic gate having a plurality of inputs, wherein... Agent: Ryan, Mason & Lewis, LLP

20080054934 - Cmos output driver: A CMOS output driver is provided for driving a capacitive load over a circuit trace in high speed applications. The CMOS output driver comprises a signal input and a signal output. The output driver has a first buffer amplifier with an input connected to the signal input and an output... Agent: Texas Instruments Incorporated

20080054940 - Circuit arrangement and method for converting logic signal levels and use of the circuit arrangement: A circuit arrangement for converting logic signal levels has a level converter and a mixing arrangement for influencing a pulse width. The level converter includes a first signal path and a second signal path each having a series circuit comprising two transistors of different conductivity types and two outputs which... Agent: Slater & Matsil LLP

20080054941 - Voltage level shifter circuit: A level shifter circuit for converting a logic signal with logic ‘1’ and ‘0’ levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In particular, the second high and low supply voltage levels are greater than the first high... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080054946 - Semiconductor integrated circuit: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains... Agent: Miles & Stockbridge PC