Electronic digital logic circuitry inventions 02/08

20080048712 - Gate driving circuit and display apparatus having the same: In a gate driving circuit and a display apparatus having the same, a ripple preventing part is connected to a pull-up part and a control terminal (Q-node) to reset the Q-node. The ripple preventing part includes a first ripple preventing device that resets the Q-node during a high period of... Agent: H.c. Park & Associates, PLC

20080048713 - Transmission/reception apparatus for differential signals: A transmission device transmits differential signals that are to be output, in the form of current signals via first and second output terminals. A first switching transistor and a first output transistor are serially connected between the grounded terminal, which is set to a fixed electric potential, and the first... Agent: Cantor Colburn, LLP

20080048720 - Data transmitters and methods thereof: In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit... Agent: Harness, Dickey & Pierce, P.L.C

20080048722 - Drive circuit: A drive circuit includes a load circuit, first and second series circuits, a bias circuit, and first and second voltage applying units. The load circuit is arranged between first and second nodes. The first series circuit is arranged between a first power supply node for supply of a first voltage... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048721 - Input buffer in ultradeep submicron process: An input buffer for an Ultradeep Sub Micron (UDSM) process which allows the UDSM process to interface with a 3V input. The input voltage is applied to a degenerated transistor which forms part of the input buffer. The input buffer effectively drops the input voltage to a voltage suitable for... Agent: Texas Instruments Incorporated

20080048725 - Domino circuit with master and slave (dual) pull down paths: A domino circuit and method include a master evaluation node to which a master discharge path with a wide input AND gate is coupled and a virtual evaluation node to which an output stage and slave discharge path are coupled. A current mirror interconnects the master discharge path and the... Agent: Ibm Corporation

20080048711 - Error correcting logic system: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the... Agent: Hoffman Warnick & D'alessandro, LLC

20080048714 - On-die termination device: An one-die termination includes: a code generator configured to generate a calibration code in response to a voltage of a first node and a reference voltage; a calibration resistor unit connected to the first node, and configured to be turned on and off in response to the calibration code; and... Agent: Mcdermott Will & Emery LLP

20080048715 - Programmable system on a chip for power-supply voltage and current monitoring and control: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring,... Agent: Sierra Patent Group, Ltd.

20080048716 - Integrated circuit including programmable logic and external-device chip-enable override control: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a... Agent: Sierra Patent Group, Ltd.

20080048717 - Programmable system on a chip: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic... Agent: Sierra Patent Group, Ltd.

20080048718 - Programmable gate array apparatus and method for switching circuits: A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048719 - Level shift circuit: A level shift circuit determining a logic value while preventing load capacitance from increasing. A voltage detector detects the states of first and second voltages and generates first and second detection signals. A first logic unit generates a first control signal having a level that is in accordance with an... Agent: Arent Fox LLP

20080048723 - Buffer circuit having electrostatic discharge protection: The buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an put/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the... Agent: Harness, Dickey & Pierce, P.L.C

20080048724 - Low power output driver: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20080042684 - Apparatus for controlling on-die termination of semiconductor memory and methods of controlling the same: An apparatus for controlling on-die termination of a semiconductor memory includes a detector that generates an ODT control signal for inactivating an on-die termination operation in one of a data read period and a data write period in response to a command signal for testing the on-die termination operation, and... Agent: Venable LLP

20080042685 - Input and output circuit: Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N1, having as load a Pch transistor P1 and resistance element R1, and an Nch transistor N2, having as load a... Agent: Scully Scott Murphy & Presser, PC

20080042686 - Electrostatic discharge protection circuit and terminating resistor circuit: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to... Agent: Arent Fox LLP

20080042687 - Programmable logic device and method for designing the same: In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first... Agent: Mcdermott Will & Emery LLP

20080042688 - Line driver device: A line driver device is provided in which an output stage can be controlled so as to provide an output current according to at least a first or a second operating mode of the line driver device, the first operating mode corresponding to a class A mode of the line... Agent: Maginot, Moore & Beck

20080042689 - Voltage buffer and source driver thereof: A voltage buffer and the source driver thereof are disclosed. The above-mentioned voltage buffer includes an operational amplifier and an overdriving unit, wherein the operational amplifier outputs an output voltage. The overdriving unit is coupled between an input voltage and the operational amplifier for comparing the input voltage with the... Agent: Jianq Chyun Intellectual Property Office

20080036490 - Semiconductor integrated circuit device with a fail-safe io circuit and electronic device including the same: A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control signal and to maintain... Agent: Lee & Morse, P.C.

20080036496 - Current mode logic-cmos converter: A current mode logic (CML)-CMOS converter comprises an input stage that is turned on/off by receiving an input voltage from the outside; a voltage control unit that outputs a constant voltage; a first switching unit that is connected to the input stage and the voltage control unit and is turned... Agent: Lowe Hauptman Ham & Berner, LLP

20080036497 - Logic gate, scan driver and organic light emitting diode display using the same: A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage... Agent: Lee & Morse, P.C.

20080036501 - Accelerated n-channel dynamic register: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes high, and pulls a pre-charged... Agent: Huffman Law Group, P.C.

20080036502 - Accelerated p-channel dynamic register: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes low, and pulls a pre-discharged... Agent: Huffman Law Group, P.C.

20080036488 - Fault tolerant integrated circuit architecture: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which... Agent: Gamburd Law Group LLC

20080036489 - Resilient integrated circuit architecture: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which... Agent: Gamburd Law Group LLC

20080036491 - Methods of reducing data dependent noise: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which... Agent: Fletcher Yoder

20080036492 - Memory module and method having improved signal routing topology: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080036493 - Element controller for a resilient integrated circuit architecture: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element... Agent: Gamburd Law Group LLC

20080036494 - Reconfigurable ic that has sections running at different looperness: Some embodiments provide a reconfigurable IC that includes at least two sections, each with several configurable circuits. Each configurable circuit configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that... Agent: Adeli & Tollen, LLP

20080036495 - Input circuit: An input circuit is provided that can identify three states of an external signal without complicated voltage adjustment and that can reduce the power consumption in a standby state. The input circuit includes: four resistor elements (3-6) serially provided between different fixed potentials; an input terminal (2) connected to a... Agent: Fish & Richardson P.C.

20080036499 - Address transition detector for fast flash memory device: An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively... Agent: Sierra Patent Group, Ltd.

20080036498 - Logic circuit, system for reducing a clock skew, and method for reducing a clock skew: A logic circuit includes a first flip-flop configured to include a first input terminal introducing a clock, a first output terminal supplying the clock and a first internal wiring connecting the first input terminal and the first output terminal, and a second flip-flop configured to be adjacent to the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080036500 - Dual control analog delay element: An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080036503 - Variable threshold transistor for the schottky fpga and multilevel storage cell flash arrays: An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays,... Agent: Sawyer Law Group LLP

20080030221 - Method of controlling on-die termination of memory devices sharing signal lines: A method of controlling On-Die Termination (ODT) resistors of memory devices sharing signal lines is provided. The ODT controlling method comprises setting an ODT control enable signal of each of the memory devices and address/command or data termination information to a mode register of the corresponding memory device, and controlling... Agent: Volentine & Whitt PLLC

20080030223 - Device and method to eliminate step response power supply perturbation: A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the... Agent: Scully Scott Murphy & Presser, PC

20080030224 - Logic with state retentive sleep mode: Embodiments disclosed herein provide sleep mode solutions for retaining state information while reducing power in a logic block.... Agent: Blakely Sokoloff Taylor & Zafman

20080030228 - Cells of a customizable logic array device having independently accessible circuit elements: Various embodiments of the invention provide for cell structures having independently accessible circuit elements as a part of a customizable logic array device. In one embodiment, a cell forming a portion of a customizable logic array device includes a base layer, which, in turn, including circuit elements each having one... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20080030229 - Fast ac coupled level translator: A level translator has a pair of transistors, wherein a first transistor of the pair of transistors and a second transistor of the pair of transistors are complimentary. A pair of capacitors are provided, wherein a first capacitor of the pair of capacitors is coupled to a voltage input VIN... Agent: Weiss & Moy PC

20080030230 - Apparatus and method to reduce voltage swing for control signals: The present invention provides for a device to reduce the voltage swing for control signals. An input signal with a maximum potential of DVDD and minimum potential of AVSS is level shifted to a maximum potential of AVDD and a minimum potential of AVDD-DVDD. A series of control signals are... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080030232 - Input/output circuit: An input/output circuit operable in input and output modes and including an input/output terminal, pull-up and pull-down output transistors, and first and second logic circuits operated in accordance with data and an enable signal. A control circuit maintains the pull-up output transistor in an inactivated state regardless of the voltage... Agent: Arent Fox LLP

20080030233 - Stacked buffers: Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor... Agent: Wolf Greenfield & Sacks, P.C.

20080030222 - Semiconductor memory device with ability to adjust impedance of data output driver: A semiconductor memory device for performing an OCD calibration control operation to adjust a data output impedance includes a decoder for decoding an address signal to generate an OCD default control signal, an OCD operation signal and plural data, a code generator for receiving plural-bit data to generate an OCD... Agent: Townsend And Townsend And Crew, LLP

20080030226 - Fpga powerup to known functional state: A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via... Agent: Hoffman, Warnick & D'alessandro LLC

20080030225 - Optically reconfigurable gate array write state inspection method, write state inspection device, and optically reconfigurable gate array: To provide a technology for inspecting a write state without requiring a dedicated circuit for write state inspection of a logical circuit in an ORGA. Upon switching an optical signal to be irradiated an optically reconfigurable bit element as an inspection target from ON to OFF, in the logical circuit... Agent: Kratz, Quintos & Hanson, LLP

20080030227 - Reconfigurable ic that has sections running at different reconfiguration rates: Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the... Agent: Adeli & Tollen, LLP

20080030231 - Level shifter and voltage converting device: A level shifter voltage contributing to a simplified interface and realizing a reduced power consumption and a voltage supplying device using such a level shifter are provided. A level shifter (1) receives an input data (Din) having a voltage of 0V (zero) and a clock signal (CLK) to shift said... Agent: Birch Stewart Kolasch & Birch

20080030234 - Logic circuit: A logic circuit is provided with a first differential transistor pair (Q1, Q2) operable in response to a data signal input thereto; a current source for supplying a current to the first differential transistor pair (Q1, Q2); a first transistor (Q5) connected between a common emitter of the first differential... Agent: Sughrue Mion, PLLC