|FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE|
USPTO Class 326 | Browse by Industry: Previous - Next | All
01/2008 | Recent | 08: Dec | Nov | Oct | Sp | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 07: D | N | O | S | A | J | J | M | A | M | F | J | | 06: 12 | 11 | 10 | 09 | 8 | 7 | 6 | 5 | 4 | Dec | Nov | | 2010 | 2009 |
Electronic digital logic circuitry January USPTO class listing 01/08Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/31/2008 > patent applications in patent subcategories. USPTO class listing
20080024161 - Automatic bus management: A method includes providing a bus, and providing a means for testing the bus for proper termination resistance during normal operation of the bus.... Agent: Fisher Patent Group, LLC
20080024160 - On-chip resistor calibration for line termination: Systems and methods for on-chip resistor calibration are disclosed. A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel.... Agent: Thomas C. Chuang
20080024164 - Reconfigurable programmable logic device with p-channel non-volatile memory cells: A system is disclosed for constructing a reconfigurable programmable logic device (PLD) comprising a first P-channel nonvolatile memory cell with a first source, a first drain and a first gate coupled to a first input node, a second P-channel nonvolatile memory cell with a second source, a second drain and... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP
20080024165 - Configurable embedded multi-port memory: Programmable routing structures to couple physical memory nodes to logical memory nodes in embedded multi-port memory FPGA's are disclosed. In a first embodiment, a plurality of physical domain nodes couples a plurality of variable node sets in a logical read domain, wherein a configuration element activates one of the sets... Agent: Raminda U. Madurawe
20080024169 - Capacitive node isolation for electrostatic discharge circuit: Capacitive node isolation circuitry in an integrated circuit eliminates the creation of hot spots (stored charge) on high capacitive nodes during a test of electrostatic discharge (ESD) protection circuitry of the integrated circuit or during any ESD event occurring while the integrated circuit is in a standby mode. The isolation... Agent: Schneck & Schneck
20080024171 - Switch sequencing circuit systems and methods: Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a driver that receives data signals and provides an output signal based on the data signals, with the driver having a plurality of transistors... Agent: Macpherson Kwok Chen & Heid LLP
20080024162 - Constant impedance cmos output buffer: The present invention provides a buffer circuit for providing constant impedance to a transmission line in an integrated circuit. The buffer circuit includes an output terminal, an input terminal, a power supply terminal, a virtual voltage terminal, a first switching element, and a second switching element. The input terminal includes... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20080024163 - Programmable logic device: Provided is a programmable logic device which increases the speed of switching the functions of a reconfigurable core by high-speed configuration data transfer. The programmable logic device includes: a configuration data storage memory which stores configuration data transferred from the outside of the programmable logic device; a reconfigurable core which... Agent: Greenblum & Bernstein, P.L.C
20080024166 - Fast/slow state machine latch: A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed... Agent: Hoffman, Warnick & D'alessandro LLC
20080024167 - Design structure for improved delay voltage level shifting for large voltage differentials: A design structure embodied in a machine readable medium used in a design process includes a voltage level shifting device for translating a lower operating voltage to a higher operating voltage, the voltage level shifting device including a first input node coupled to a first pull down device and a... Agent: Cantor Colburn LLP - IBM Rochester Division
20080024168 - High speed transceiver with low power consumption: High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.... Agent: Ivy Y. Mei
20080024170 - Design structure for high speed differential receiver with an integrated multiplexer input: A design structure embodied in a machine readable medium used in a design process includes high-speed interface between a first network component and a second network component, the interface including a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first... Agent: Cantor Colburn LLP - IBM Rochester Division
20080024172 - Actively compensated buffering for high speed current mode logic data path: An actively compensated CML circuit includes a CML buffer circuit and a bandwidth expansion circuit. The CML buffer circuit includes a first MOS transistor and a second MOS transistor in a differential pair configuration. A first load resistor is coupled to a first MOS transistor drain at a first output... Agent: Thomas C. Chuang01/24/2008 > patent applications in patent subcategories. USPTO class listing
20080018357 - Automatic termination circuit: An automatic termination circuit is disclosed. The automatic termination circuit includes an adjustable termination resistance device having an output terminal for connecting the adjustable termination resistance device to a transmission line, wherein the adjustable termination resistance device has an associated termination resistance. The automatic termination circuit is operable to automatically... Agent: Honeywell International Inc.
20080018358 - Circuit and method for power management: A semiconductor network is interposed between first and second multiple-port interfaces each having high-voltage, intermediate-voltage and ground ports to form a switch assembly. The assembly includes a primary switch circuit, a support network, internal and external-port circuits and internal and external-port control circuits. The primary switch circuit is coupled to... Agent: Smith Frohwein Tempel Greenlee Blaha, LLC
20080018360 - High speed voltage level shifter circuits: A level shifter circuit for shifting a voltage level of a logic signal from a first voltage to a second voltage includes an input stage operating in a domain of a first voltage supply that receives an input signal. The input stage includes a first inverter receiving the input signal... Agent: Ibm Corporation RochesterIPLaw Dept 917
20080018359 - Configurable ic's with configurable logic resources that have asymmetric inputs and/or outputs: Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set... Agent: Adeli Law Group, A Professional Law Corporation
20080018361 - Semiconductor integrated circuit and method of fabricating the same: A semiconductor integrated circuit includes a MOS logic operating by first and second voltages; a switching transistor unit disposed between a supply terminal of the first voltage or the second voltage and the MOS logic, and turned on or off in response to a control signal so as to control... Agent: F. Chau & Associates, LLC01/17/2008 > patent applications in patent subcategories. USPTO class listing
20080012598 - Apparatus and method for controlling a driver strength: Method of controlling a driver strength and a termination impedance of a signal line of an interface, wherein the driver sends an output signal as an alternating voltage with a frequency, wherein the signal line is terminated with a termination impedance, wherein the driver strength is changed depending on a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda
20080012597 - Method for controlling the evaluation time of a state machine: A method for protecting a state machine having an operation modeled by a set of states linked to each other by transitions, the state machine evaluating output signals upon each transition during an evaluation phase according to input signals comprising signals evaluated during a previous transition, the method comprising steps... Agent: Seed Intellectual Property Law Group PLLC
20080012599 - Modal interval processor: A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.... Agent: Nawrocki, Rooney & Sivertson Suite 401, Broadway Place East
20080012600 - Current-controlled cmos circuits with inductive broadbanding: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional... Agent: Garlick Harrison & Markison
20080012601 - Semiconductor integrated circuit: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H level.... Agent: Mcdermott Will & Emery LLP01/10/2008 > patent applications in patent subcategories. USPTO class listing
20080007294 - Input circuits and methods thereof: An input circuit comprising a level-determining unit and an output unit is provided. In a first period controlled by a first enable signal, the level-determining unit receives an input signal at an input terminal of the input circuit and determines a voltage level of the input signal. The output unit... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20080007296 - Liquid crystal display device and electronic device: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal... Agent: Fish & Richardson P.C.
20080007297 - Fan abnormality detection device: When a fan drive current has become excessive, a fan drive device intercepts that current, waits for just a fixed time period T1, and thereafter flows that current for a second time. The fan power supply current flowed to the fan drive device is detected by a shunt resistor R.... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20080007298 - A level shift circuit: A level shift circuit is used to receive a low-voltage signal to generate a corresponding high-voltage signal. The circuit has a first transistor of a first type, a second transistor of a second type, a third transistor of the second type and a fourth transistor of the second type. The... Agent: Patterson & Sheridan, L.L.P.
20080007299 - Power generation circuit: In a power generation circuit configured by a voltage follower amplifier, a selector is provided inside of an operation amplifier. When a standby mode is released, a bias voltage in a constant current source is applied to a gate of a PMOS, and during a normal operation, an output voltage... Agent: Nixon Peabody, LLP
20080007301 - Single gate oxide level shifter: A level shifter includes a first inverter coupled between the second voltage and the first voltage, and a second inverter coupled between the second voltage and the first voltage, the second inverter being cross-coupled with the first inverter for latching a value therein. A first switch module is coupled between... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP
20080007302 - Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode: Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of... Agent: Pillsbury Winthrop Shaw Pittman LLP
20080007303 - Semiconductor device: A semiconductor device includes a first input terminal, the first input terminal being supplied with an input signal, an input detection circuit including a delay circuit having a second input terminal and an output terminal, the input detection circuit detecting a shift in the input signal and generating a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20080007288 - Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects... Agent: Sierra Patent Group, Ltd.
20080007289 - Semiconductor device capable of adjusting output impedance of external semiconductor device and output impedance adjusting method: In a semiconductor device capable of adjusting an output impedance of a first output impedance adjustable output buffer of an external semiconductor device connectable to the semiconductor device, a second output impedance adjustable output buffer is provided. A comparator compares a first output voltage of a real load circuit including... Agent: Mcginn Intellectual Property Law Group, PLLC
20080007290 - Semiconductor device with bus terminating function: The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output transistor, which drives an output node in accordance with an internal signal. The area of... Agent: Mcdermott Will & Emery LLP
20080007291 - Non-volatile look-up table for an fpga: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc... Agent: Sierra Patent Group, Ltd.
20080007292 - Non-volatile look-up table for an fpga: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc... Agent: Sierra Patent Group, Ltd.
20080007293 - Non-volatile look-up table for an fpga: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC... Agent: Sierra Patent Group, Ltd.
20080007295 - Tri-stated driver for bandwidth-limited load: A CMOS driver circuit is configured to provide a tri-state condition after a predetermined number of like-valued data bits have been transmitted, reducing the presence of intersymbol interference (ISI) along a transmission channel. In situations where the transmission channel is bandwidth-limited, the use of the tri-stating technique allows for the... Agent: Wendy W. Koba
20080007300 - Method and apparatus for buffering bi-directional open drain signal lines: A buffer system includes a logic adjusting circuit for translating a first logic level of a first component to a second logic level of a second component. The first and second logic level values are substantially different, and the buffer system has no directional control signal. A method of interfacing... Agent: Edell, Shapiro & Finnan, LLCPrevious industry: Electricity: measuring and testing
Next industry: Miscellaneous active electrical nonlinear devices, circuits, and systems
RSS FEED for 20130516:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electronic digital logic circuitry patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electronic digital logic circuitry patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electronic digital logic circuitry patents we recommend signing up for free keyword monitoring by email.
FreshPatents.com Support - Terms & Conditions
Results in 0.32308 seconds