Electronic digital logic circuitry inventions 12/07

20070296458 - Fault tolerant integrated circuit architecture: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which... Agent: Gamburd Law Group LLC

20070296459 - Resilient integrated circuit architecture: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which... Agent: Gamburd Law Group LLC

20070296460 - Semiconductor apparatus and signal processing system: A semiconductor apparatus of the present invention includes a first to a fourth external terminals and a decoding circuit. The semiconductor apparatus in a first mode inputs a first encoded data from the first external terminal, decodes a second encoded data by the decoding circuit to generate a first decoded... Agent: Young & Thompson

20070296461 - System, method and apparatus for transmitting and receiving a transition minimized differential signal: The present invention is directed to a system, method, and apparatus to transmit/receive TMDS signals using general purpose differential transmitter and receivers. In an embodiment, the general purpose differential transmitter and receivers are designed to operate with differential signaling schemes such as LVDS and LVPECL. In one aspect, embodiments according... Agent: Fiala & Weaver, P.l.l.c. C/o Intellevate

20070296463 - Driver with variable output voltage and current: A driver circuit with variable output voltage and current. A source input terminal of the driver circuit may receive a source control signal. A voltage control circuit may drive one of the terminals of a first switch to a source voltage. If the source input terminal receives an asserted source... Agent: Jeffrey C. Hood Meyertons Hood Kivlin Kowert & Goetzel PC

20070296464 - Methods and apparatus for serially connected devices: Apparatus and methods for processing a clock input signal with a clock regeneration circuit to provide a clock output signal for coupling to a cascaded device. The clock output signal has a period substantially equal to the period of the clock input signal and a duty cycle independent of the... Agent: Daly, Crowley, Mofford & Durkee, LLP

20070296465 - Domino logic testing systems and methods: A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic node, and an output inverter for inverting an output of the dynamic node. A logic network is coupled to the dynamic node for discharging the dynamic node in accordance with logic. A footer device... Agent: Polsinelli Shalton Flanigan Suelthaus PC

20070296455 - Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a... Agent: Mcdermott Will & Emery LLP

20070296456 - Low-power ethernet transmitter: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070296457 - Programmable logic circuit control apparatus, programmable logic circuit control method and program: Disclosed is a programmable logic circuit control apparatus capable of managing data with various bit widths and data lengths, generated by various processes to be executed by a programmable logic circuit, with a simple structure. A module address memory section (4) stores data indicating addresses of modules or conditions for... Agent: Baker & Mckenzie LLP Patent Department

20070296462 - Logic circuit for high-side gate driver: A logic circuit for high-side gate driver includes a p-MOSFET array connected to a first voltage source, an n-MOSFET array connected to a second voltage source, and a resistor arranged between the p-MOSFET array and the n-MOSFET array, wherein a first node between the resistor and at least one of... Agent: Sidley Austin LLP

20070290711 - Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control: The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070290713 - Input termination circuitry with high impedance at power off: An input termination circuit includes a first and a second resistor each having a terminal respectively coupled to a first and a second input terminal of the input termination circuit, a first and a second transistor coupled in series between the first resistor and the second resistor, and a third... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070290712 - Switch selectable terminator for differential and pseudo-differential signaling: An active terminator is configured with switches to select between terminating two lines for transmitting one differential signal pair or two single ended signals terminated in a pseudo-differential receiver. The receiver circuitry is configured with three differential comparators. One differential comparator receives both signal lines and other two differential comparators... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20070290715 - Method and system for using one-time programmable (otp) read-only memory (rom) to configure chip usage features: Aspects of a method and system for using one-time programmable (OTP) read-only memory (ROM) to configure chip usage features are presented. Aspects of the system may include a one time programmable (OTP) memory on a chip that is configured to enable control of access to on-chip functions provided by on-chip... Agent: Mcandrews Held & Malloy, Ltd

20070290716 - Multiplexing circuit for decreasing output delay time of output signal: Disclosed herein is a multiplexing circuit for decreasing the output delay time of an output signal. The multiplexing circuit includes multiplexing units and a multiplexing output unit. Each multiplexing unit is initialized in response to an initialization signal, and outputs an input signal as a selection output signal in response... Agent: Lowe Hauptman Ham & Berner, LLP

20070290718 - Semiconductor device: In normal operation, an internal circuit 4 operates in synchronism with a clock CK, so that switching operation of the output circuit 2 is performed based on inputted data and an output enable signal. At this point, an output from the internal circuit 4 to a three-state control circuit 3... Agent: Birch Stewart Kolasch & Birch

20070290719 - N-domino register with accelerated non-discharge path: An N-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a... Agent: Huffman Law Group, P.C.

20070290720 - P-domino register with accelerated non-charge path: A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a... Agent: Huffman Law Group, P.C.

20070290714 - Calibration methods and circuits to calibrate drive current and termination impedance: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing... Agent: Silicon Edge Law Group, LLP

20070290717 - Digital logic unit reconfigurable in nonvolatile fashion: A circuit analyzes the configured status of cells with a magnetic layer system, resistance of which may be altered by magnetic field pulses, forming a first line branch with data cells arranged in series and a second line branch with configurable cells arranged in series. The circuit includes a difference... Agent: Staas & Halsey LLP

20070285118 - Semiconductor integrated circuit device: To strengthen tolerance to radiation. Source and back gate of P-channel transistor P1 are connected to power supply. Gate of the P-channel transistor P1 is connected to input terminal IN. Drain of P1 is connected to output terminal OUT. Source and back gate of N-channel transistor N1 are grounded. Gate... Agent: Young & Thompson

20070285120 - Configurable voltage mode transmitted architecture with common-mode adjustment and novel pre-emphasis: Configurable voltage mode transmitter architectures are based on combinations of drive cells and parallel termination cells connected in parallel across an external load to provide configurable output characteristics. Each drive cell and parallel termination can be individually enabled, various configurations of enabled cells providing the output characteristics configurability. In some... Agent: Dr. Mark M. Friedman C/o Bill Polkinghorn - Discovery Dispatch

20070285121 - Reference voltage generators for reducing and/or eliminating termination mismatch: A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits... Agent: Lee & Morse, P.C.

20070285122 - on-chip supply regulators: Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control... Agent: Ivy Y. Mei

20070285128 - Differential line termination technique: A technique for terminating a differential signal line substantially matches the output impedances of a first node and a second node of a differential node. The power dissipation is substantially less than twice the power delivered to a load impedance coupled to the differential signal line. The technique provides a... Agent: Zagorin O'brien Graham LLP

20070285130 - Floating driving circuit: A floating driving circuit according to the present invention comprises an input circuit to receive an input signal. A latch circuit receives a trigger signal for generating a latch signal. The latch signal is used to turn on/off a switch. A coupling capacitor is connected between the input circuit and... Agent: Rosenberg, Klein & Lee

20070285129 - Signal transmitting circuit: An exemplary signal transmitting circuit includes a drive circuit, a receiving circuit, and a filter circuit coupled between the drive circuit and the receiving circuit. The filter circuit includes a first photocoupler having a first luminous element and a first optical receiving block, an anode of the first luminous element... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070285119 - Combinatorial logic circuit: It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply currents (111, 112). The circuit further comprises a second logic block... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070285123 - Programming semiconductor dies for pin map compatibility: Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or... Agent: Kacvinsky LLC C/o Intellevate

20070285126 - Architecture for routing resources in a field programmable gate array: A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a... Agent: Sierra Patent Group, Ltd.

20070285124 - Embedding memory between tile arrangement of a configurable ic: Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable... Agent: Adeli Law Group, A Professional Law Corporation

20070285125 - Method and apparatus for accessing stored data in a reconfigurable ic: Some embodiments provide a first interconnect circuit for accessing stored data in a reconfigurable IC. The reconfigurable IC has at least one reconfigurable circuit and a set of storage elements for storing several data sets for the particular reconfigurable circuit. The first interconnect circuit includes second, third, and fourth interconnect... Agent: Adeli Law Group, A Professional Law Corporation

20070285127 - Programmable array logic circuit employing non-volatile ferromagnetic memory cells: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no... Agent: Morgan Lewis & Bockius LLP

20070285131 - Sense amplifier circuit and sense amplifier-based flip-flop having the same: A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input... Agent: F. Chau & Associates, LLC

20070279084 - Integrated circuit with graduated on-die termination: An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data... Agent: Shemwell Mahamedi LLP

20070279086 - Antifuse programming circuit with snapback select transistor: An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the antifuse and has a gate terminal coupled to receive a first select signal. The select transistor operates in... Agent: Williams, Morgan & Amerson

20070279087 - Reconfigurable integrated circuit device to automatically configure an initialization circuit: A reconfigurable integrated circuit device which is configured to an arbitrary computation state based on configuration data has a reconfiguration circuit unit, having a plurality of processor elements which are reconfigurable and a processor element network which connects the processor elements in an arbitrary state; and, a configuration control section,... Agent: Staas & Halsey LLP

20070279088 - T-switch buffer, in particular for fpga architectures: An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20070279093 - Level shift circuit and display device having the same: A liquid crystal display (“LCD”) includes a first voltage shift circuit at a front stage of an inverter circuit. The first voltage shift circuit includes a second transistor having a source serving as an input, and a gate and drain connected to each other, and is operated as a diode,... Agent: Cantor Colburn, LLP

20070279092 - Level shifter circuit: A level shifter is disclosed. The level shifter includes a level shifter core circuit and a pull-up control logic circuit. In response to an input signal and an output signal of the level shifter core circuit, the pull-up control logic circuit selectively turns on a transistor within the level shifter... Agent: Dillon & Yudell LLP

20070279097 - High-speed low-power integrated circuit interconnects: Methods and apparatuses to decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments comprise a method to reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070279094 - Low-voltage differential signal driver for high-speed digital transmission: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases... Agent: Baker Botts L.L.P.

20070279095 - Low-voltage differential signal driver for high-speed digital transmission: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, wherein a resistance of the first converter is variable. A second converter couples to the first converter, the second converter... Agent: Baker Botts L.L.P.

20070279098 - Low-voltage differential signal driver for high-speed digital transmission: A low-voltage differential signal (LVDS) driver includes at least two programmable fingers operable to drive a signal and at least two pre-drivers. Each pre-driver is associated with one or more of the programmable fingers and is operable to enable or disable the associated one or more programmable fingers. An enabled... Agent: Baker Botts L.L.P.

20070279099 - Transceiver and method of operating an electrical circuit: There is provided a transceiver comprising a first node for receiving a received signal and transmitting a transmitted signal; a receiver, connected between a first voltage and the first node, for processing the received signal; a transmitter, connected between a second voltage and the first node, for generating the transmitted... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070279096 - Usb 2.0 transmitter using only 2.5 volt cmos devices: A USB transmitter 3.3V output stage includes a PMOS cascode transistor connected between a PMOS pullup transistor and a USB port data pin, an NMOS cascode transistor connected between an NMOS pulldown transistor and the data pin, and an output driver circuit that generates a pullup signal range of 0.8V... Agent: Bever, Hoffman & Harms, LLP

20070279100 - Recycling charge to reduce energy consumption during mode transition in muiltithreshold complementary metal-oxide-semiconductor (mtcmos) circuits: In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transistor, and a virtual supply node... Agent: Baker Botts L.L.P.

20070279082 - Semiconductor integrated circuit: A semiconductor integrated circuit comprises logic cones having a structure in which substrates thereof are isolated from each other and substrate potentials can be controlled, and a potential switching section for supplying a substrate voltage from any of a first substrate bias supply potential and a second substrate bias supply... Agent: Mcdermott Will & Emery LLP

20070279083 - Buffer circuit with output signal slope control means: A buffer circuit for transmission of logical signals includes a first buffer and second buffer. The first buffer supplies logical signals to the output buffer which is connected in series with the first buffer to produce output logical signals. A slope of the logical signals produced at the output of... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20070279085 - Programmable logic circuit: A programmable logic circuit (100) includes a processor element (101) having: a logic cell (300) which can modify the function according to first setting information and generates data by performing a predetermined logic calculation on an input signal; a cross connect switch (301) for generating data by performing alignment, copying,... Agent: Stevens, Davis, Miller & Mosher, LLP

20070279089 - Reconfigurable integrated circuits with scalable architecture including one or more adders: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070279090 - Logic basic cell: A logic basic cell contains a first logic function block and a second logic function block for the logic combination of a first input signal and a second input signal in accordance with a predeterminable first or second logic subfunction, and a first logic transistor coupled to the first logic... Agent: Dickstein Shapiro LLP

20070279091 - Digital voltage level shifter: A digital voltage level shifter for converting an input signal with a low voltage swing to an output signal with a high voltage swing comprises a first inverter stage for generating an inverted signal from an input signal, the inverted signal having a voltage swing between a core voltage and... Agent: Slater & Matsil