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Electronic digital logic circuitry November USPTO class patent listing 11/07Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/29/2007 > patent applications in patent subcategories. USPTO class patent listing
20070273403 - Clock tree for programmable logic array devices: A clock tree for PLAD is provided, with each logic element having an embedded circuit having a buffer connecting vertical bus wires to horizontal bus wires so that the clocks on each horizontal bus wire are synchronized, because the every horizontal wire gets the same capacitor and the same clock... Agent: Lin & Associates Intellectual Property, Inc.
20070273404 - Mixed voltage input/output buffer having low-voltage design: A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving... Agent: Bucknam And Archer
20070273407 - Data processing circuit: The present invention provides a semiconductor device including a resistive element having a resistance characteristic which is not influenced by fluctuations in power supply voltage and a signal output circuit having a desired output impedance characteristic without being influenced by fluctuations in power supply voltage. A constant current based on... Agent: Miles & Stockbridge PC
20070273406 - Input circuit for semiconductor integrated circuit: An input circuit for a semiconductor integrated circuit in which an operational state is constant even when a process condition, a temperature, a voltage, and the like are varied at the time of operation is provided. The input circuit includes a first input unit that performs a first amplifying operation... Agent: Venable LLP
20070273401 - Systems and methods for improved fault coverage of lbist testing: Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) by determining weighting and/or seed values to be used in generating pseudorandom test bit patterns for each channel to optimize fault coverage. In one embodiment, a method includes generating a pseudorandom sequence of bits, applying... Agent: Law Offices Of Mark L. Berrier
20070273402 - Relational signaling and medium for high speed serial communications: Three or more wires are configured as a differential “skein” (FIG. 1). Symbols may use equal voltages as well as differing voltages. “Softpairs” (132 142 152) of a “skein” are discriminated in differential mode by “relational comparators” (200), exploiting hysteresis in differential comparators to detect voltage near-equality versus signed difference.... Agent: David Zethmayr Aka Jon David Zethmayr
20070273405 - Voltage divider circuit: The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least one source driver IC. In addition, a first terminal... Agent: Jianq Chyun Intellectual Property Office
20070273408 - Random number generation based on logic circuits with feedback: A random binary sequence generator for generating a random binary sequence adapted to be used for producing random numbers, includes at least one logic circuit corresponding to an associated finite-state machine having a state-transition function including states arranged to form cycles of states, wherein the at least one logic circuit... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP11/22/2007 > patent applications in patent subcategories. USPTO class patent listing
20070268039 - Programmable impedance control circuit calibrated at voh, vol level: A method and apparatus are provided for a programmable impedance control circuit. In one example of the apparatus, a programmable impedance control circuit of an output driver of an input/output interface is provided. The programmable impedance control circuit includes a pull-up impedance programmed according to a multi-stage emulator and a... Agent: Jonathan O. Owens Haverstock & Owens LLP
20070268040 - Logic circuit system and method of changing operating voltage of a programmable logic circuit: A logic circuit system, having a programmable logic circuit including a circuit configuration including a first set of plural unit circuits and that is reconfigurable during operation, a circuit configuration information supplier configured to supply circuit configuration information about a second set of plural unit circuits to said programmable logic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20070268041 - Scalable non-blocking switching network for programmable logic: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors in each set of the second plurality of conductors substantially connect,... Agent: Daniel E. Ovanezian Blakely, Sokoloff, Taylor & Zafman LLP
20070268042 - Memory based computation systems and methods of using the same: A high performance memory based computation system comprises an array of memory cells. Each memory cell stores a logic data corresponding to a chosen combination of inputs based on a specific logic function. For improved performance, the memory cell array can be divided into sub-blocks; and the sub-blocks can be... Agent: Watchstone P+d, PLC
20070268043 - Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply... Agent: Advanced Micro Devices, Inc. C/o Vedder Price Kaufman & Kammholz, P.C.
20070268044 - Output buffer and method having a supply voltage insensitive slew rate: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP11/15/2007 > patent applications in patent subcategories. USPTO class patent listing
20070262786 - Fault tolerant asynchronous circuits: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single—event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.... Agent: Jlb Consulting, Inc. C/o Intellevate
20070262790 - Level shifting circuit for semiconductor device: A level shifting circuit for a semiconductor device comprises a controller, a level shifting portion, and a driving portion. The controller is adapted to level shift a power converting input signal having a first voltage level to generate a pair of control signals having different logic levels from each other.... Agent: Volentine & Whitt PLLC
20070262787 - Soft error tolerant flip flops: A register designed to detect and correct soft errors in real time. A redundant latch is added to the existing structure of a flip flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voting circuit. If the content... Agent: Patterson & Sheridan, LLP/ Lucent Technologies, Inc
20070262788 - Circuit system: A circuit system includes: a master node; and a slave portion including a plurality of non-grounded slave nodes, each of which couples with the master node through a pair of communication lines. The master node and the slave portion provide a differential transmission system for differentially transmitting a signal among... Agent: Harness, Dickey & Pierce, P.L.C
20070262789 - Logic array devices having complex macro-cell architecture and methods facilitating use of same: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The... Agent: Tillman Wright, PLLC
20070262791 - Integrated circuit to store a datum: An integrated circuit includes a programmable circuit with a programmable element, and a storage circuit to store a storage state depending on a programming state of the programmable element of the programmable circuit unit. The storage circuit includes a first inverter circuit and a second inverter circuit. The strengthening and... Agent: Edell, Shapiro & Finnan, LLC
20070262792 - Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (cmos) and strained/unstrained silicon-on-insulator (soi): The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon... Agent: Rana, Amar Pal Singh
20070262793 - Circuit configurations having four terminal jfet devices: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.... Agent: Walker & Sako, LLP Suite 23511/08/2007 > patent applications in patent subcategories. USPTO class patent listing
20070257707 - Semiconductor integrated circuit: In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a... Agent: Mcdermott Will & Emery LLP
20070257699 - Multi-memory module circuit topology: A multi-memory module circuit topology is disclosed that includes a memory controller, a plurality of memory modules connected to the memory controller through a memory bus, and a resonator connected to the plurality of memory modules in a starburst topology. A method for reducing impedance discontinuities in a multi-memory module... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP
20070257702 - Hybrid configurable circuit for a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit has: (1) a set of inputs,... Agent: Adeli Law Group, A Professional Law Corporation
20070257701 - Integrated circuit comprising a test mode secured by the use of an identifier, and associated method: An electronic circuit includes configurable cells capable of being functionally linked to logic cells with which they cooperate to form at least one logic circuit if a chaining command signal is in a first (inactive) state. The electronic circuit also includes a logic interconnection circuit for performing the following functions... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20070257703 - Logic circuit system and method of changing operating voltage of a programmable logic circuit: A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070257700 - Method and apparatus for decomposing functions in a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least... Agent: Adeli Law Group, A Professional Law Corporation
20070257704 - Programmable crossbar signal processor used as morphware: A method includes providing a crossbar array including a programmable material layer, wherein the crossbar array is configured to function as part of a signal processing system and reprogramming at least one impedance value of the programmable material layer formed at crosspoints of the crossbar array to change the signal... Agent: Blaise Mouttet
20070257705 - Device for managing the consumption peak of a domain on each powering-up: A device is provided for managing the current consumption peak on each powering-up of a domain in an electronic circuit. A plurality of domains are present and a global power supply grid provides power. Each domain is selectively supplied by a local supply grid connected to the global supply grid... Agent: Gardere Wynne Sewell LLP Intellectual Property Section
20070257706 - Cmos output driver using floating wells to prevent leakage current: An I/O buffer circuit including: a driver circuit containing a pull-up device in a first floating well and a pull-down device in a second floating well; a first and second biasing circuits to bias the first and second floating wells in response to voltages internal and external to the I/O... Agent: Cantor Colburn LLP-ibm Burlington11/01/2007 > patent applications in patent subcategories. USPTO class patent listing
20070252615 - Logic-keeping apparatus for improving system-level electrostatic discharge robustness: A logic-keeping apparatus including a logic judgment unit and a noise-event detection unit is disclosed. When the level at the input terminal of the logic judgment unit is larger than a first level, the output terminal thereof outputs a first logic state; when the level at the input terminal is... Agent: Jianq Chyun Intellectual Property Office
20070252616 - Programmable system on a chip for temperature monitoring and control: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with... Agent: Sierra Patent Group, Ltd.
20070252617 - Versatile logic element and logic array block: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the... Agent: Beyer Weaver LLP Attn: Altera
20070252619 - Differential current-mode driver with high common-mode range and controlled edge rates: A differential current-mode driver that meets the IEEE 1394 standard employs a wide output range in common-mode voltage, minimizes timing skew over this wide range, and has well-controlled rise/fall times in the edge rates of the digital signals transmitted, within the window specified by the IEEE 1394 standard, without having... Agent: Lsi Corporation
20070252618 - Signal converter circuit: A signal converter circuit including an input circuit and an output circuit. The input circuit is configured to receive current mode logic signals and provide differential input signals based on the current mode logic signals. The output circuit is configured to receive the differential input signals and provide rail-to-rail output... Agent: Dicke, Billig & CzajaPrevious industry: Electricity: measuring and testing
Next industry: Miscellaneous active electrical nonlinear devices, circuits, and systems
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