Electronic digital logic circuitry inventions 10/07

20070247185 - Memory system with dynamic termination: The termination impedance of a memory agent may be selected dynamically. A transmission line may be simultaneously terminated with a first impedance at first memory agent and a different impedance at a second memory agent. A memory agent may have a terminator with at least two termination values and logic... Agent: Intel Corporation C/o Intellevate, LLC

20070247191 - Pre-emphasis automatic adjusting method and data transmission system using same: A signal transmission system is provided which is capable of simplifying circuits and shortening time required for automatic adjustment of pre-emphasis. A signal having a single pulse pattern is generated by a single pulse pattern generating circuit. A signal having passed through a selector is divided into two signals whose... Agent: Mcginn Intellectual Property Law Group, PLLC

20070247192 - Open drain output circuit: An open drain output circuit for use as an I2C bus interface. The open drain output circuit includes an output terminal. An input unit performs a first operation causing the potential at the output node to steeply fall and a second operation for gradually raising the potential in accordance with... Agent: Arent Fox PLLC

20070247193 - Output buffer circuit and system including the output buffer circuit: An output buffer circuit, which minimizes or prevents output delay of output signal and degradation of slew rate while suppressing overshoot and undershoot, is provided. In a first time period when an input signal to a gate of an N-channel output transistor changes from ‘L’ level to ‘H’ level, the... Agent: Oliff & Berridge, PLC

20070247195 - Low output-to-output skew/low jitter staggered output buffer: A system and method for generating multiple current steered output signals at a centralized location and subsequently routing them to their respective output pads is shown and described. The system and method allow designers to variously stagger output pad configurations while maintaining low output-to-output skew and low jitter.... Agent: Marger Johnson & Mccollom, P.C.

20070247182 - Protection of security key information: A protection circuit is disclosed, for preventing access to stored security key data after the security key is no longer used. The protection circuit performs operations on a programming circuit used to program a bit of the security key. The protection circuit prevents inspection of the security key bit, using... Agent: Carrie A. Boone, P.C.

20070247183 - Logic-latching apparatus for improving system-level electrostatic discharge robustness: A logic-latching apparatus includes a noise-event detection unit, a combinational logic unit and a latch unit. The noise-event detection unit is used for detecting whether or not a noise-event occurs (for example, an ESD). The latch unit is coupled with the noise-event detection unit and the combinational logic unit for... Agent: Jianq Chyun Intellectual Property Office

20070247184 - Serial communications bus with active pullup: A dual-wire communications bus circuit, compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to one or more slave devices and a... Agent: Schneck & Schneck

20070247186 - Semiconductor integrated circuits with power reduction mechanism: A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit block includes a first MOS transistor in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070247187 - Apparatus and method for remotely powering a data acquisition or utilization device: Apparatus for delivering operating power from a data terminus to a utilization device includes a first data connection connecting the data terminus to a data repeater station and a second data connection connecting the data repeater station to the utilization device. A first power sourcing equipment delivers DC operating power... Agent: Smith-hill And Bedell, P.C.

20070247188 - Programmable semiconductor device: A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional... Agent: Foley And Lardner LLP Suite 500

20070247189 - Field programmable semiconductor object array integrated circuit: A field-programmable object array integrated circuit employs a course gain architecture comprising a core array of highly optimized silicon objects that are individually programmed and synchronously connected via high performance parallel communications structures permitting the user to configure the device to implement a variety of very high performance algorithms. The... Agent: Stoel Rives LLP

20070247190 - Dual voltage single gate oxide i/o circuit with high voltage stress tolerance: An I/O output circuit is disclosed for interfacing a first system operating at a first voltage with a second system operating at a second voltage higher than the first voltage. The I/O output circuit includes an output stage module having one or more PMOS transistors and one or more NMOS... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070247194 - Output buffer to drive ac-coupled terminated transmission lines: An output buffer for driving an AC-coupled resistively terminated transmission line comprises at least first and second drive circuits coupled to an input signal and providing respective drive signals that transition in response to respective transitions of the input signal. The buffer is arranged such that, in response to a... Agent: Koppel, Patrick & Heybl

20070247196 - Circuit and method for configuring a circuit: A circuit and method for configuring a circuit is disclosed. In one embodiment, the circuit includes at least one pull-down path, wherein an amount of a current flowing through the pull-down path is determined by a switchable resistivity value of a switchable resistor that is included by the circuit. The... Agent: Dicke, Billig & Czaja

20070247197 - Multi-write memory circuit with a data input and a clock input: Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the feedback loop at multiple points, and propagated in parallel from those points to other points in the... Agent: Wagner, Murabito & Hao LLP

20070241769 - Usb device and data processing system having the same: A universal serial bus (USB) device is comprised of a receiver for receiving signals from a USB host through data lines, and a pull-up resistor circuit connecting pull-up resistors to data lines in response to control signals. The pull-up resistor circuit selectively connects a plurality of pull-up resistors with a... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070241787 - Configurable circuits, ic's, and systems: Some embodiments of the invention provide a first configurable integrated circuit (IC) that has a first configurable IC design. The first configurable IC implements a second IC design that is specified for a second IC that is to operate a particular design rate. The first configurable IC includes several configurable... Agent: Adeli Law Group, A Professional Law Corporation

20070241786 - Configurable integrated circuit with different connection schemes: Some embodiments provide an IC with a configurable node array that has (1) two similar nodes within the interior of the array, and (2) two different connection schemes. The first connection scheme specifies a set of connections between the first node and a set of nodes in the array, while... Agent: Adeli Law Group, A Professional Law Corporation

20070241791 - Non-sequentially configurable ic: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures... Agent: Adeli Law Group, A Professional Law Corporation

20070241768 - Changing chip function based on fuse states: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070241777 - Configurable circuits, ic's and systems: Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection schemes for communicatively coupling the input terminal set to the output terminal... Agent: Adeli Law Group, A Professional Law Corporation

20070241771 - Configurable circuits, ic's, and systems: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform... Agent: Adeli Law Group, A Professional Law Corporation

20070241770 - Configurable integrated circuit with built-in turns: Some embodiments provide a configurable integrated circuit (“IC”) with a configurable node array. A configurable node array may include configurable nodes arranged in rows and columns. It may also include direct offset connections, with each direct offset connection connecting two nodes that are neither in the same column nor the... Agent: Adeli Law Group, A Professional Law Corporation

20070241776 - Configurable logic circuits with commutative properties: Some embodiments of the invention provide a configurable logic circuit. The logic circuits has inputs for receiving input data. It also has a first connecting circuit for receiving configuration data and at least a portion of the input data. Based at least partially on the received portion of the input... Agent: Adeli Law Group, A Professional Law Corporation

20070241772 - Embedding memory within tile arrangement of a configurable ic: Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably... Agent: Adeli Law Group, A Professional Law Corporation

20070241773 - Hybrid logic/interconnect circuit in a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic... Agent: Adeli Law Group, A Professional Law Corporation

20070241778 - Ic with configurable storage circuits: Some embodiments of the invention provide a reconfigurable IC that has several reconfigurable circuits. Each reconfigurable circuit for configurably performing a set of operations and for reconfiguring at a first frequency. The reconfigurable IC also has at least one reconfiguration signal generator for receiving a clock signal at a second... Agent: Adeli Law Group, A Professional Law Corporation

20070241774 - Reconfigurable ic that has sections running at different looperness: Some embodiments provide a reconfigurable IC that includes at least two sections, each with several configurable circuits. Each configurable circuit configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that... Agent: Adeli Law Group, A Professional Law Corporation

20070241779 - Semiconductor integrated circuit: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are... Agent: Rader Fishman & Grauer PLLC

20070241775 - Storage elements for a configurable ic and method and apparatus for accessing data stored in the storage elements: Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the... Agent: Adeli Law Group, A Professional Law Corporation

20070241780 - Reconfigurable ic that has sections running at different reconfiguration rates: Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which of which configurably performs a set of operations, Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation... Agent: Adeli Law Group, A Professional Law Corporation

20070241782 - Configurable ic with interconnect circuits that also perform storage operations: Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurable routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each... Agent: Adeli Law Group, A Professional Law Corporation

20070241784 - Configurable ic with interconnect circuits that have select lines driven by user signals: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes a first set of circuits and a second set of circuits interspersed among the first set of circuits. Each set of circuits includes at least ten volatile configurable circuits. Several circuits in at least one of... Agent: Adeli Law Group, A Professional Law Corporation

20070241783 - Configurable ic with routing circuits with offset connections: Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a... Agent: Adeli Law Group, A Professional Law Corporation

20070241785 - Configurable ic's with logic resources with offset connections: A configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a... Agent: Adeli Law Group, A Professional Law Corporation

20070241789 - Configurable integrated circuit with offset connection: Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in... Agent: Adeli Law Group, A Professional Law Corporation

20070241790 - Semiconductor integrated circuit: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are... Agent: Rader Fishman & Grauer PLLC

20070241781 - Variable width management for a memory of a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes several non-configurable memories for storing and outputting data. The IC also includes several configurable logic circuits that each can configurably perform a set of functions, and several configurable interconnect circuits that each can configurably perform a... Agent: Adeli Law Group, A Professional Law Corporation

20070241788 - Vpa logic circuits: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving... Agent: Adeli Law Group, A Professional Law Corporation

20070241792 - Apparatus for hysteresis based process compensation for cmos receiver circuits: A process compensation circuit for an inverting element of a CMOS device, including a duplicate inverting element connected in parallel with the inverting element of the CMOS device. An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the... Agent: Cantor Colburn LLP-ibm Burlington

20070236248 - Apparatus for on-die termination of semiconductor memory and method of operating the same: The apparatus for on-die termination of a semiconductor memory includes a first ODT (On-Die Termination) voltage generating unit that outputs a first line voltage by calibrating an input voltage with a resistance ratio according to a first code having at least two bits; a first code calibrating unit that counts... Agent: Venable LLP

20070236251 - Level-shifting apparatus and panel display apparatus using the same: A level-shifting apparatus and a panel display apparatus using the same are disclosed. The level-shifting apparatus is used for receiving and changing the level of an input signal to generate an output signal. The level-shifting apparatus includes a first unit and a second unit. The first unit is for deciding... Agent: Jianq Chyun Intellectual Property Office

20070236252 - Impedance converting circuit and electronic device: A semiconductor circuit including an input terminal, an impedance converting portion configured to receive an input signal from the input terminal and to output an output signal corresponding to the input signal, an input impedance of the semiconductor circuit being higher than an output impedance of the semiconductor circuit, a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070236245 - Superconductive crossbar switch: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality... Agent: Dla Piper US LLP

20070236246 - Radiation hardened differential output buffer: A radiation hardened differential output buffer is partitioned into multiple stages, each including at least one current source and a bridge circuit. Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output. The outputs of each stage are connected together. As a... Agent: Honeywell International Inc.

20070236247 - Techniques for providing flexible on-chip termination control on integrated circuits: On-chip termination (OCT)calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control... Agent: Steven J. Cahill

20070236249 - Minimizing timing skew among chip level outputs for registered output signals: A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously... Agent: Bever, Hoffman & Harms, LLP

20070236250 - Enhanced scheme to implement an interconnection fabric using switching networks in hierarchy: An interconnection fabric using switching networks organized in multiple levels of hierarchy to allow flexible interconnections of the switching networks amongst different levels of hierarchy and on the same level of hierarchy. The resulting interconnection fabric can be used in electronic devices, such as switching networks, routers, and programmable logic... Agent: Blakely Sokoloff Taylor & Zafman

20070236253 - Semiconductor integrated circuit: A semiconductor integrated circuit comprising: a logic section having a plurality of first transistors; a second transistor, having source and drain electrodes connected between a first reference voltage line and a first reference voltage line side terminal of the logic section, and having a gate electrode to which a control... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070236254 - Zero clock delay metastability filtering circuit: A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge detection circuit coupled to the sampling circuit for... Agent: Kramer & Amado, P.C.

20070236255 - High speed differential receiver with an integrated multiplexer input: A high-speed interface between a first network component and a second network component includes a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the... Agent: Cantor Colburn LLP - IBM Rochester Division

20070229112 - Programmable crossbar signal processor with op-amp outputs: A device including a crossbar array including a programmable material layer and an array of op-amps connected to outputs of the crossbar array.... Agent: Blaise Mouttet #110-364

20070229111 - Programmable crossbar signal processor with rectification layer: A device includes a rectifying layer having a first side and a second side, a first array of wires formed above the first side of the rectifying layer, and a second array of wires formed below the second side of the rectifying layer.... Agent: Blaise Mouttet

20070229113 - Analog voltage recovery circuit: In an embodiment, an analog voltage recovery circuit comprising a plurality of capacitors having first terminals connected to a node having the analog voltage, and comprising a state machine, where during an operating mode the second terminals of the plurality of capacitors are coupled to a first rail, and where... Agent: Intellevate 900 Second Avenue South

20070229114 - Interconnections for plural and hierarchical p1500 test wrappers: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides... Agent: Texas Instruments Incorporated

20070229115 - Method and apparatus for correcting duty cycle error in a clock distribution network: A clock distribution network for distributing a repetitive timing signal throughout an integrated circuit, the timing signal being within a range of frequencies about a first frequency, includes multiple buffer circuits and at least one conductive segment connecting one of the buffers to another of the buffers. The conductive segment... Agent: Ryan, Mason & Lewis, LLP

20070229116 - Apparatus for implementing dynamic data path with interlocked keeper and restore devices: A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second... Agent: Cantor Colburn LLP-ibm Burlington