Electronic digital logic circuitry inventions 09/07

20070222476 - Semiconductor memory device testing on/off state of on-die-termination circuit during data read mode, and test method of the state of on-die-termination circuit: A semiconductor memory device for testing whether an ODT circuit is on or off during a data read mode includes an on-die termination (ODT) circuit and an ODT state information output unit. The ODT circuit includes at least one ODT resistor. The ODT state information output unit outputs an ODT... Agent: Mills & Onello LLP

20070222479 - Complementary signal generating circuit: A complementary signal generating circuit according to an embodiment of the present invention includes: an inverting element inverting a first signal to generate a second signal; a first transistor connecting a first power supply potential and a first output terminal electrically in accordance with the first signal; a second transistor... Agent: Mcginn Intellectual Property Law Group, PLLC

20070222475 - Low swing current mode logic family: The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic block during an evaluation phase; and, a feedback path arranged... Agent: Bacon & Thomas, PLLC

20070222477 - Fracturable lookup table and logic element: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexes with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs... Agent: Beyer Weaver LLP Attn: Altera

20070222478 - Voltage level shift circuit: A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and... Agent: J.c. Patents, Inc.

20070222480 - Circuit and method for latch bypass: A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value.... Agent: Larson Newman Abel Polansky & White, LLP

20070216444 - Interface circuit and control method thereof: This invention provides an interface circuit for detecting that a DQS signal from a DDR SDRAM is at an intermediate potential. An interface circuit is connected to at least a signal line which transmits the DQS signal from the DDR SDRAM and reaches an intermediate potential VM when the signal... Agent: Arent Fox PLLC

20070216441 - Terminating resistance adjusting method, semiconductor integrated circuit and semiconductor device: A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit. The method includes obtaining a comparison result by comparing a reference voltage and a voltage of a first node that is coupled to a first voltage via a current supply circuit, the first voltage being one... Agent: Arent Fox PLLC

20070216442 - Low-leakage level shifter with integrated firewall and method: A level shifter may reduce leakage current and provide firewall protection between circuits of different voltage domains when one voltage domain is in a standby mode. The level shifter may either couple or decouple input circuitry from a reference voltage in response to a firewall enable signal, may translate signal... Agent: Oliff & Berridge, PLC

20070216443 - High speed voltage translator circuit: A high speed voltage translator circuit includes a voltage divider coupled between first and second power supplies, a transconductance amplifier coupled between third and fourth power supplies including a non-inverting voltage input coupled to the voltage divider, an inverting voltage input for receiving an input signal, and a current output,... Agent: Hogan & Hartson LLP

20070216445 - Output buffer with switchable output impedance: An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode,... Agent: Koppel, Patrick & Heybl

20070216446 - Complementary output inverter: A complementary output driver includes a driver input that receives an input signal which alternates between a first state and a second state. A first inverter has a first input and a first output. The first input is coupled to the driver input and the first output generates a complementary... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070210825 - Tri-state circuit using nanotube switching elements: Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tri-stated, which state allows interconnection to a common bus or other shared communication lines.... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070210827 - Application-specific integrated circuit equivalents of programmable logic and associated methods: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070210826 - Programmable logic devices comprising time multiplexed programmable interconnect: Time-multiplexed interconnect structures, timing optimization techniques and software tools for said structures, for programmable semiconductor ICs is disclosed. A first aspect is a programmable logic device, wherein a plurality of outputs from logic blocks is coupled to a plurality of inputs to logic blocks by a single wire segment comprising... Agent: Raminda U. Madurawe

20070210829 - Block symmetrization in a field programmable gate array: An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels,... Agent: Sierra Patent Group, Ltd.

20070210828 - Input device for an electronic device and electronic device having the same: An input device for an electronic device is provided that includes a base, a frame pivotally connected to the base, a roller member rotatably supported by the frame, and at least one button pivotally connected at a side of the base. An electronic device is also provided that includes a... Agent: Birch Stewart Kolasch & Birch

20070210830 - Three dimensional integrated circuits: In a first aspect, a three-dimensional semiconductor device, wherein: a configurable memory element coupled to a programmable logic circuit to program the logic circuit is positioned substantially above the logic circuit. In a second aspect, a three-dimensional semiconductor device, comprising: a first module layer having a circuit block; and a... Agent: Raminda U. Madurawe

20070210831 - Circuit and method to balance delays through true and complement phases of differential and complementary drivers: A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay device coupled to an input... Agent: Texas Instruments Incorporated

20070210833 - Method and apparatus for reducing clock enable setup time in a multi-enabled clock gating circuit: A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one... Agent: Qualcomm Incorporated

20070210832 - Method and apparatus for slew rate control: Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the data paths... Agent: Ryan, Mason & Lewis, LLP

20070205806 - Open-drain output circuit: A pulse generation section generates a pulse which is at H-level for the predetermined period of time from the timing of the input signal DATA changing to L-level. A main output section outputs a signal of L-level with transistors P1, N1, and N2 turned ON, while the pulse generation section... Agent: Foley And Lardner LLP Suite 500

20070205799 - Radiation hardened logic circuit: A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry can be a controlled pass-gate circuit and a data latch, an adjustable... Agent: Hogan & Hartson LLP

20070205800 - High-voltage tolerant power-rail esd clamp circuit for mixed-voltage i/o interface: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070205801 - Latch-up prevention circuitry for integrated circuits with transistor body biasing: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute... Agent: G. Victor Treyz

20070205802 - Adjustable transistor body bias generation circuitry with latch-up prevention: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe... Agent: G. Victor Treyz

20070205803 - System for signal routing line aggregation in a field-programmable gate array: An aggregation interconnect scheme for a programmable logic device provides low-skew routing of high fan-out signals by aggregating regional routing resources, which provide low-skew routing utilizing under-utilized global routing resources.... Agent: Sierra Patent Group, Ltd.

20070205805 - Electrical system including driver that provides a first drive strength and a second drive strength: An electrical system including a signal line and a driver. The signal line is terminated via a passive component. The driver is configured to receive an input signal and provide an output signal via the signal line. The driver is configured to provide an output logic level in the output... Agent: Dicke, Billig & Czaja

20070205804 - Multi-bit configuration pins: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data input signal in response to a first control signal and a second control signal. The second circuit may be configured to (i) generate the first control signal and the second... Agent: Lsi Corporation