Electronic digital logic circuitry inventions 08/07

20070200592 - Dynamic output buffer circuit: A dynamic output buffer circuit performs an impedance matching function and a pre-emphasis function by using input and output signals, and consumes relatively less power, occupies a relatively smaller layout area, and dynamically varies an output impedance. The dynamic output buffer circuit dynamically matches an output impedance to the characteristic... Agent: Mills & Onello LLP

20070200591 - Method and apparatus for high resolution zq calibration: A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device.... Agent: Jones Day

20070200593 - Digital circuit with dynamic power and performance control via per-block selectable operating voltage: A digital circuit with dynamic power and performance control via per-block selectable operating voltage level permits dynamic tailoring of operating power to processing demand and/or compensation for process variation. A set of processing blocks having a power supply selectable from two different power supply voltage levels is provided. The power... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070200594 - High bandwidth reconfigurable on-chip network for reconfigurable systems: A crossbar switch is implemented in a reconfigurable circuit, such as a FPGA, instantiated with a number of modules, the crossbar switch providing communication links between the modules. The modules and crossbar switch can be easily updated in a partial reconfiguration process changing only portions of modules and the crossbar... Agent: Xilinx, Inc Attn: Legal Department

20070200595 - Apparatus and method for reducing power consumption in electronic devices: An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal based on the switch values. The clock control signal controls a macrocell... Agent: Volpe And Koenig, P.C.

20070200596 - Apparatus and methods for adjusting performance of programmable logic devices: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.... Agent: Law Offices Of Maximilian R. Peterson

20070200597 - Clock generator having improved deskewer: Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, differences in delay time, referred to... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070200598 - Low voltage output buffer and method for buffering digital output data: Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer (12) having first and second inputs and an output and at least one N-type isolation transistor (13,... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070194805 - Data output driving circuit of semiconductor memory apparatus: A data output driving circuit includes a plurality of driving units that are set to have different impedance values from one another, and the number of driving units is less than the number of a plurality of required driving impedance values such that the driving units can obtain the plurality... Agent: Venable LLP

20070194808 - High-performance static programmable logic array: A high-performance programmable logic array (PLA) includes an AND plane that is initialized when a reset signal is activated and that evaluates a plurality of input signals when the reset signal is inactivated; and or OR plane that receives output signals of the AND plane, that is disabled when one... Agent: F. Chau & Associates, LLC

20070194804 - Electronic device and method: A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer... Agent: Larson Newman Abel Polansky & White, LLP

20070194806 - Reconfigurable digital logic unit: The invention relates to a reconfigurable digital logic unit comprising at least one logic gate with a cell presenting a magnetic layer system, the resistance of which may be altered by means of magnetic field pulses. Said logic gate comprises at least one first leg with at least one data... Agent: Young & Thompson

20070194807 - Packet-oriented communication in reconfigurable circuit(s): A reconfigurable circuit having communication resources configured to facilitate selective packet-oriented communications among reconfigurable resources is described herein.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070194809 - Output stage with low output impedance and operating from a low power supply: A low-impedance output stage which operates from a low voltage power supply. In an embodiment, the output stage contains an operational amplifier and two PMOS transistors used in a feedback configuration resulting in low output impedance. The output stage may also include a capacitor connected between the output terminal of... Agent: Texas Instruments Incorporated

20070194810 - Locally asynchronous, block-level synchronous, configurable logic blocks with sub-threshold analog circuits: Embodiments utilize analog sub-threshold circuits to perform Boolean logic and soft-gate logic. These analog circuits may be grouped into configurable logic blocks that are locally asynchronous, but block-level synchronous. The Boolean logic, or function, performed by these blocks may be configured by programming bits. Other embodiments are described and claimed.... Agent: Intellevate 900 Second Avenue South

20070188194 - Level shifter circuit and method thereof: A level shifter circuit and method thereof are provided. The example level shifter circuit may include a pull-up drive unit driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage... Agent: Harness, Dickey & Pierce, P.L.C

20070188186 - Systems and methods for managing power supplied to integrated circuits: Systems and methods for reducing power consumed by digital circuits using an off-chip controller to selectively provide power to individual portions of the circuitry. One embodiment comprises an IC and an off-chip power controller. The circuitry constructed on the IC chip includes two or more independently powered regions. The power... Agent: Law Offices Of Mark L. Berrier

20070188187 - Impedance matching and trimming apparatuses and methods using programmable resistance devices: Impedance matching and trimming apparatuses and methods using programmable resistance devices. According to one exemplary embodiment, the impedance matching circuit includes a programmable resistance element, a comparator, a resistor divider having a common node coupled to a first input of the comparator, and an impedance element control circuit coupled between... Agent: Patent Law Professionals

20070188188 - Structured integrated circuit device: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with... Agent: Connolly Bove Lodge & Hutz LLP

20070188190 - Antifuse circuit: An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions... Agent: Freescale Semiconductor, Inc. Law Department

20070188189 - Programmable logic device with serial interconnect: In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070188191 - Differential amplifier with over-voltage protection and method: Circuitry for preventing damage to bipolar transistors in integrated circuit amplifier circuitry during slew-limited operation includes first and second transistors, each having first, second, and third electrodes, a first one of the first and second electrodes of the first transistor being coupled to receive a first signal, and a first... Agent: Texas Instruments Incorporated

20070188192 - Level shift circuit: To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second inverters 300 and 200 of a CMOS type in which... Agent: Mcdermott Will & Emery LLP

20070188193 - Low-voltage-to-high-voltage level converter for digital signals and related integrated circuit, system, and method: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is... Agent: Graybeal Jackson Haley LLP

20070188195 - Driver for multi-voltage island/core architecture: A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses... Agent: Hoffman, Warnick & D'alessandro LLC

20070188196 - Bootstrap inverter circuit: A bootstrap inverter circuit, consisting of transistors of the same type, comprises a first transistor, a second transistor, a voltage clamp circuit and an output end. The voltage clamp circuit, having a first node and a second node, controls the voltage of a gate of the second transistor. A gate... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20070188197 - Flip-flop circuit and frequency divider using the flip-flop circuit: In a flip-flop circuit where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the conductivity of a first load transistor connected to the first output terminal is controlled by the signal from the second output terminal, and the conductivity of... Agent: Volentine & Whitt PLLC

20070182444 - Semiconductor integrated circuit device: Disclosed is a semiconductor integrated circuit device that includes an output circuit with power thereof supplied from one power supply system, an input circuit with an input terminal thereof connected to an output terminal of the output circuit through a signal line and with power thereof supplied from other power... Agent: Mcginn Intellectual Property Law Group, PLLC

20070182448 - Level shifter for flat panel display device: A level shifter for a flat panel display device is provided. The level shifter includes a first transistor coupled with a first power supply and having a gate and a drain are coupled together; and a capacitor coupled between an input voltage terminal and a first node coupled with the... Agent: Christie, Parker & Hale, LLP

20070182451 - Data input/output circuit and method of semiconductor memory apparatus: A first timing control unit controls an active timing of a first control signal to output a first driving control signal. A first data input/output unit transmits write data from a data input/output buffer to a global input/output line or transmits read data from the global input/output line to the... Agent: Venable LLP

20070182453 - Circuit and method for outputting data in semiconductor memory apparatus: A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in active periods of rising and falling clocks, respectively, in accordance with a state of an output enable signal. A main driver generates last output data to... Agent: Venable LLP

20070182445 - Efficient configuration of daisy-chained programmable logic devices: In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into... Agent: Macpherson Kwok Chen & Heid LLP

20070182446 - Synchronous first-in/first-out block memory for a field programmable gate array: The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random... Agent: Sierra Patent Group, Ltd.

20070182447 - Capacitor-coupled level shifter with duty-cycle independence: A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power... Agent: Raymond J. Werner

20070182449 - Level shifting multiplexing circuit for connecting a two conductor full duplex bus to a bidirectional single conductor bus: A level shifting multiplexing circuit provides an interface between a two conductor full duplex bus (two conductor bus) and a single conductor bidirectional half duplex bus (single conductor bus) where the two conductor bus is operates at a first supply voltage and the single conductor bus operates at a second... Agent: Kyocera Wireless Corp.

20070182450 - Voltage level shifter circuit: A level shifter circuit for converting a logic signal with logic ‘1’ and ‘0’ levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In particular, the second high and low supply voltage levels are greater than the first high... Agent: Borden Ladner Gervais LLP

20070182452 - Transmitter circuit, receiver circuit, interface circuit, and electronic instrument: A transmitter circuit including: a current driver which current-drives differential signal lines; and a voltage driver which is electrically disconnected from at least one of the differential signal lines in a normal transfer mode, and is electrically connected to the at least one of the differential signal lines and voltage-drives... Agent: Oliff & Berridge, PLC

20070182454 - Input buffer with optimal biasing and method thereof: A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input... Agent: Trask Britt, P.C./ Micron Technology

20070182455 - And type match circuit structure for content-addressable memories: This invention provides An AND type match circuit structure for content-addressable memories adopting the Pseudo-Footless Clock-and-Data Pre-charged Dynamic circuit as an AND type match circuit structure, which comprises a plurality of circuit stages. Each circuit stage connects a CMOS to a plurality of NMOS in series, wherein the CMOS is... Agent: Rosenberg, Klein & Lee

20070182456 - Reducing pin count when the digital output is to be provided in differential or single-ended form: An integrated circuit provides digital output signals in either single-ended or differential form on a shared set of pins. A control circuit generates signals to ensure that when one form (single-ended or differential) of outputs are being provided, outputs in the other form are disabled. Outputs in differential form may... Agent: Texas Instruments Incorporated

20070176627 - Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets: An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and... Agent: National Aeronautics And Space Administration Langley Research Center

20070176636 - Power supply circuit and control method thereof: A power supply circuit and a control method are provided, in which the original enable pad and output pad, or the enable pad and feedback pad are used to trim the output voltage of the power supply circuit without extra trim pads.... Agent: Rosenberg, Klein & Lee

20070176638 - Output driver that operates both in a differential mode and in a single mode: An output driver of a semiconductor memory device that operates in a differential mode and in a single mode is disclosed. The output driver includes a current supplying circuit that operates as a resistor in a single mode and as a current source in a differential mode. Accordingly, the semiconductor... Agent: Mills & Onello LLP

20070176640 - Dynamic circuit: The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a control circuit for outputting a control signal of which the logic level changes according to the result... Agent: Mcdermott Will & Emery LLP

20070176641 - Low swing domino logic circuits: e

20070176642 - Domino logic circuit techniques for suppressing subthreshold and gate oxide leakage: Circuits are provided for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and a dual threshold voltage CMOS technology may be utilized to place idle domino logic circuits into a low leakage state. The circuits may significantly lower the total leakage power... Agent: Brinks Hofer Gilson & Lione

20070176628 - Semiconductor integrated circuit: A semiconductor integrated circuit for matching the resistance of a variable resistor, which is used as a terminating resistor or a reference of said terminating resistor, to the characteristic impedance of a transmission line, has a terminating resistor adjusting circuit that has a current circuit connected to a power supply,... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070176629 - Molecular electronic device having organic conducting electrode as protective layer: Provide is a molecular electronic device which includes a first electrode, a molecular active layer self-assembled on the first electrode using a thiol-based anchoring group or a silane-based anchoring group, and a second electrode including an organic electrode layer covering the molecular active layer. The organic electrode layer includes a... Agent: Mayer, Brown, Rowe & Maw LLP

20070176630 - Fpga architecture at conventional and submicron scales: Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input... Agent: Hewlett Packard Company

20070176631 - Programmable system on a chip: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic... Agent: Sierra Patent Group, Ltd.

20070176632 - Integrated circuit package, and a method for producing an integrated circuit package having two dies with input and output terminals of integrated circuits of the dies directly addressable for testing of the package: An integrated circuit package (1) comprising first and second dies on a laminate (5) in a resin encapsulating housing (6) comprises a digital signal processing integrated circuit (8) fabricated on the first die (2), and a digital-to-analogue converting circuit (9) fabricated on the second die (3). First external terminals (16)... Agent: Wolf Greenfield & Sacks, P.C.

20070176633 - Output circuit: An output circuit including: a tri-state output circuit capable of outputting high-impedance state, high-level state, and low-level state, in which the high-level state and low-level state are low-impedance state, and switching the high-impedance state and the low-impedance state in accordance with a first control signal; and a delay circuit outputting... Agent: Arent Fox PLLC

20070176634 - Transistor arrangement, integrated circuit and method for operating field effect transistors: The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in... Agent: Dicke, Billig & Czaja

20070176635 - Voltage level translator circuit with wide supply voltage range: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated... Agent: Ryan, Mason & Lewis, LLP

20070176637 - Motor driving circuit: In a motor driving circuit in which a first NMOS and a second NMOS coupled in series to the final output stage to drive a motor are driven and a common node of the source of the first NMOS and the drain of the second NMOS serves as the final... Agent: Fish & Richardson P.C.

20070176639 - Low leakage and data retention circuitry: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal... Agent: Carr & Ferrell LLP

20070176643 - Universal logic gate utilizing nanotechnology: A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create A plasticity mechanism is also provided, which is based on a plasticity rule for... Agent: Ortiz & Lopez, PLLC Patent Attorneys

20070176644 - Programmable logic function generator using non-volatile programmable memory switches: Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus employ programmable switches to emulate memory units that are used in LUTs... Agent: Perkins Coie LLP Patent-sea