Electronic digital logic circuitry inventions 07/07

20070170952 - Quasi-particle interferometry for logical gates: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for v=5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we... Agent: Woodcock Washburn LLP (microsoft Corporation)

20070170953 - System and method for extending universal bus line length: A system and method for recovering a high frequency component of a slew rate controlled signal propagating along a transmission line enables the high frequency component to be recovered after being lost because of slew rate control and transmission line low pass filtering effects. The system includes a wave shaping... Agent: Honeywell International Inc.

20070170955 - High voltage tolerant output buffer: A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed... Agent: Hogan & Hartson LLP

20070170954 - Semiconductor integrated circuit: A driver circuit for a signal line of a large load is configured to include: a pMOS transistor having a source and a drain connected with a signal line and a ground line, respectively, and a gate receiving an input signal; and an nMOS transistor having a source and a... Agent: Arent Fox PLLC

20070164780 - Apparatus for controlling on-die termination: An on-die termination control unit turns on/off a corresponding transistor according to a code signal and adjusts an on-die termination resistance so it is equal to an external resistance. An offset compensating unit detects an offset voltage from an output voltage of the on-die termination control unit, stores the detected... Agent: Venable LLP

20070164777 - Scan cell for an integrated circuit: A scan cell and a method for detecting supply voltage degradation in an integrated circuit using the scan cell. The scan cell includes a voltage comparator and a scan flip-flop. The voltage comparator compares a supply voltage with a reference voltage to generate a comparator output signal. The scan flip-flop... Agent: Freescale Semiconductor, Inc. Law Department

20070164778 - Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same: A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mode trigger signal on an output. In response to the... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070164779 - Feedback circuit for line load compensation and reflection reduction: Line load compensation and reflection reduction in a signal transmitting circuit is provided using feedback capacitors. The feedback capacitor serially coupled with a resistance generates an RC rise/fall time that is independent of the line load. Additionally, by selecting a capacitor that yields a rise/fall time of approximately ⅓ of... Agent: Honeywell International Inc.

20070164781 - Component with a logic circuit arrangement with configurable functionality: A component with a logic circuit arrangement with configurable functionality, includes several data lines (7), whereby at least a part of the data lines (7) is provided with at least one element (1) which may be switched between two states with different discrete resistances. The data line (7) is opened... Agent: Young & Thompson

20070164786 - Field programmable gate array long line routing network: A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of... Agent: Sierra Patent Group, Ltd.

20070164785 - Low-power fpga circuits and methods: Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration... Agent: John P. O'banion O'banion & Ritchey LLP

20070164784 - Modular i/o bank architecture: A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O type are compatible within the same programmable device and between different... Agent: Townsend And Townsend And Crew LLP/ 015114

20070164782 - Multi-word word wheeling: The claimed subject matter provides systems and/or methods that expand input data. An interface can obtain input data and a wildcard insertion component can modify the input data to include at least one implicit wildcard inserted at an end of each intended word. Additionally, an expansion component can generate a... Agent: Amin. Turocy & Calvin, LLP

20070164783 - Reconfigurable integrated circuits with scalable architecture including one or more adders: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070164787 - Method and apparatus for late timing transition detection: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.... Agent: Blakely Sokoloff Taylor & Zafman

20070164788 - Semiconductor device and electric apparatus: A semiconductor device of an embodiment of the invention has a package substrate, and a semiconductor chip mounted on the package substrate. The semiconductor chip has an output section, and a filter section for decreasing the electromagnetic noise generated from the data communication path. The output section outputs a data... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070164789 - High speed level shift circuit with reduced skew and method for level shifting: An improved level shift circuit and method for level shifting is disclosed herein. In general, the improved level shift circuit adds a pulse generator, a feedback transistor and a latch to a conventional cross-coupled level shift circuit configuration. The pulse generator and feedback transistor are configured for reducing a fall... Agent: Daffer Mcdaniel LLP

20070164790 - Method for forming a domino circuit: A method for forming a domino circuit includes forming a pre-charge circuit in a basic unit positioned on a semiconductor body of an integrated circuit, forming elements of a pull down network circuit in the basic unit, and forming a metal layer upon the semiconductor body for routing the elements... Agent: North America Intellectual Property Corporation

20070159210 - Operation mode setting circuit, lsi having operation mode setting circuit, and operation mode setting method: According to one embodiment, a logical circuit performs an AND operation based on a mode signal input via a mode terminal and a signal formed by delaying a system reset signal as much as one clock during system reset. The logical circuit outputs a signal indicating a usual operation mode... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070159211 - Circuit for inspecting semiconductor device and inspecting method: It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is connected to one input terminal of... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070159212 - High efficiency two stage inverter: In a two stage inverter providing power to a load, a first stage component is operable to receive a first voltage input and a first control input to generate a first voltage output, which is higher than the first voltage input. The first control input is indicative of the power... Agent: Haynes And Boone, LLP

20070152706 - Semiconductor integrated circuit: A semiconductor integrated circuit with low power consumption is provided. In one embodiment, the semiconductor integrated circuit includes a logic circuit portion that is connected between a first power line and a virtual ground line. The logic circuit portion includes at least one NMOS transistor having a first threshold voltage... Agent: Marger Johnson & Mccollom, P.C.

20070152703 - Detecting counterfeit products: In some embodiments an indication of an intended use of a logic device is stored in a register of the logic device, and any further programming of the register is prevented. Other embodiments are described and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20070152704 - Method for calibrating a driver and on-die termination of a synchronous memory device: An improved driver and ODT impedance calibration techniques of a synchronous memory device are provided. The impedance calibration is performed by generating a calibration enable signal showing a calibration operation mode entry. The code signals for an ODT calibration are generated for every predetermined interval of time. A first control... Agent: Ladas & Parry LLP

20070152705 - Transmission circuit, data transfer control device and electronic equipment: To provide a transmission circuit which can adequately perform a fast data transmission even to a receiving circuit of a host controller or a device controller with a low sensitivity. A transmission circuit transmitting a signal through first and second signal lines that form a differential pair and includes a... Agent: Oliff & Berridge, PLC

20070152707 - Integrated circuits with ram and rom fabrication options: The present invention relates to electronic integrated circuits (ICs) that retain identical functionality with better performance or lower power dissipation under RAM and hard-wire ROM fabrication options, without the need to alter transistor layout within the IC. An integrated circuit (IC) comprising: a plurality of transistors; and a first selectable... Agent: Raminda U. Madurawe

20070152708 - Mpga products based on a prototype fpga: A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA;... Agent: Raminda U. Madurawe

20070152709 - Safety system based on reconfigurable array of logic gates: An array of logic gates is configured to implement a predefined strategy for an emergency response system in a hardware-only runtime environment. The array of logic gates receives a plurality of input signals from a set of sensors and actuators located within an industrial processing system. Based upon the received... Agent: Honeywell International Inc.

20070152710 - Single and composite binary and multi-valued logic functions from gates and inverters: Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states.... Agent: Diehl Servilla LLC

20070152711 - Level shifter output buffer circuit usable as an isolation cell: A level shifter output buffer circuit which converts a first operating voltage into a second operating voltage and outputs a converted voltage to an output terminal. A level shifter output buffer circuit may include at least one of: a first level shifter configured to receive an enable signal as an... Agent: Sherr & Nourse, PLLC

20070152712 - I/o cell capable of finely controlling drive strength related application: Disclosed is an I/O cell for providing an output pad with an output signal, including a first drive circuit for providing the output pad with an output signal having a drive strength which is equal to a drive strength required by a basic PMOS transistor or a basic NMOS transistor,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070152713 - Magnetic transistor with the or/nor/nand/and functions: A magnetic transistor circuit with the OR, NOR, NAND and AND functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070152714 - Logic circuit: The present invention relates to a logic circuit comprising a first and a second circuits coupled in series between two voltage levels, wherein the first circuit includes a plurality of first transistors coupled in parallel and each adapted to receive an input signal; the second circuit includes a plurality of... Agent: Bacon & Thomas, PLLC