Electronic digital logic circuitry inventions 06/07

20070146004 - On-die termination circuit and method for semiconductor memory apparatus: An on-die termination circuit for semiconductor memory apparatus includes an ODT (On Die Termination) input driving unit that divides an input voltage on the basis of a resistance ratio according to a first code Pcode<0:N> having at least two bits and outputs a first line voltage, a first ODT control... Agent: Venable LLP

20070146008 - Semiconductor circuit comprising vertical transistor: A semiconductor circuit comprising a vertical transistor is disclosed. A differential amplifier circuit comprises a pair of amplification transistors, wherein the pair of amplification transistors comprises a first amplification transistor adapted to receive, amplify, and output a differential input signal. The first amplification transistor is a first vertical transistor comprising... Agent: Volentine Francos, & Whitt PLLC

20070146005 - System and method for configuring information handling system integrated circuits: Processing components to manufacture information handling systems have build-to-order integrated circuits with plural selectively-enabled features set at the information handling system manufacture location. For instance, fuses integrated in the integrated circuits are selectively blown at the information handling system manufacture location to permanently disable features so that the processing components... Agent: Hamilton & Terrile, LLP

20070146006 - Circuit for generating precision soft-start frequency for either value of address bit applied to external reset pin: A multi-function circuit has as single input/control pin, to which respectively different values of a control input may be applied. A multi-function signal generation section is coupled to the single input/control pin and is operative to controllably generate a plurality of respectively different functional outputs, including a decoded address bit-representative... Agent: Akerman Senterfitt

20070146007 - Level shift delay equalization circuit and methodology: Transition delays in a level shift circuit are equalized by generating a first signal related to the state of the input signal, a second signal inversely related to the state of the input signal, and a third signal that is reciprocal to the second signal. Upon transition of the input... Agent: Mcdermott Will & Emery LLP

20070146009 - Apparatus for controlling drive current in semiconductor integrated circuit devices: A circuit device for variously controlling a current drive capacity of a semiconductor IC device as required by the user. A circuit device, capable of preventing a semiconductor IC device from failing to drive an external device, preventing an operational speed of the semiconductor IC device from being reduced, and... Agent: Sherr & Nourse, PLLC

20070146010 - Current supply circuit, ring oscillator, nonvolatile semiconductor device and electronic card and electronic device: A current supply circuit is disclosed, which comprises a first circuit configured to generate a first current having a positive dependence with respect to a power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, a second circuit configured to generate... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070146011 - Duty cycle adjustment: Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock signal through a clock path. A feedback circuit is coupled (i) to the clock path to monitor offset... Agent: Intel Corporation C/o Intellevate, LLC

20070146012 - Reconfigurable logic structures: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements... Agent: Thelen Reid Brown Raysman & Steiner LLP

20070146013 - Dynamic logic with adaptive keeper: Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled... Agent: Intel Corporation C/o Intellevate, LLC

20070139070 - Buffer having predriver to help improve symmetry of rise and fall transitions in an output signal: For one disclosed embodiment, a driver may generate an output signal on a line. A predriver may receive an input signal and control the driver in response to the input signal to help improve symmetry of rise and fall transitions in the output signal. Other embodiments are also disclosed.... Agent: Intel Corporation C/o Intellevate, LLC

20070139071 - Configurable on-die termination: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels... Agent: Silicon Edge Law Group, LLP

20070139072 - Semiconductor integrated circuit device: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for... Agent: Miles & Stockbridge PC

20070139074 - Configurable circuits with microcontrollers: Configurable circuits with microcontrollers are described herein. The microcontrollers may perform a variety of functions including the control of configurations of the configurable circuits.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070139073 - Pulsed flop with embedded logic: In one embodiment, an apparatus comprises a logic circuit, a plurality of passgates, at least one pulse generator, and a plurality of latch elements. The logic circuit has a plurality of inputs, and each of the passgates has an output directly connected to one of the inputs. The pulse generator... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070139075 - Combined multiplexor/flop: In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070139076 - Input/output circuit for handling unconnected i/o pads: A circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of... Agent: Patent Law Group LLP

20070139077 - Level shifter with reduced leakage current and block driver for nonvolatile semiconductor memory device: A level shifter is disclosed and generates an output signal having a swing voltage shifted by a positive boost voltage with respect to an input signal. The level shifter comprises; an enable unit adapted to enable the output signal in response to the input signal, and a disable unit adapted... Agent: Volentine Francos, & Whitt PLLC

20070139078 - Pcml driver for lvds receiver loads: The improved PCML communications driver corrects current loss and reduced voltage swing when driving an LVDS receiver load by reducing the value of the Rt1 resistors. By changing the value of the two Rt1 resistors from Rt1 to Rt1/2 (or lower), the full bias current can be restored and voltage... Agent: Pete Scott, Senior Corporate Counsel Lsi Logic Corporation

20070139079 - Reducing power noise in differential drivers: An improvement reducing or eliminating noise between drivers connected in common on a single chip. A DC power source (VDD1) providing a common signal to multiple PCML drivers and inductance introduced between a common DC power source and each of the multiple PCML drivers tied in common to the DC... Agent: Pete Scott, Senior Corporate Counsel Lsi Logic Corporation

20070139080 - Single-ended cmos signal interface to differential signal receiver loads: The interface of a single-ended CMOS type signal to differential signal loads includes a LVDS load having a +Vin input and a −Vin input, a CMOS circuit having an output signal line, and a resistor Rt connected to the output signal line and ground. A 2.5 volt source line is... Agent: Pete Scott, Senior Corporate Counsel Lsi Logic Corporation

20070139081 - Address transition detector for fast flash memory device: An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively... Agent: Sierra Patent Group, Ltd.

20070139082 - Method and apparatus for implementing subthreshold leakage reduction in lsdl: A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070132481 - Programmable josephson voltage standard device employing microwave driving of multiple frequencies: The present invention relates to a finely programmable Josephson voltage standard device employing microwave driving of multiple frequencies. To this end, the programmable Josephson voltage standard device includes a first element group 10a having the plurality of Josephson junctions 2 connected in series and applied with a first frequency f1;... Agent: Duane Morris LLP

20070132482 - Apparatus and methods for programmable logic devices with improved performance characteristics: Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.... Agent: Law Offices Of Maximilian R. Peterson

20070132483 - Bidirectional current-mode transceiver: A bidirectional current-mode transceiver is provided for improving transmission rates on a transmission line in a manner of current signal transmission, and for reducing the swing of the voltage signal on the transmission line by using a termination resistor, thus improving operating speed. Therefore, the provided transceiver can be applied... Agent: Harness, Dickey & Pierce, P.L.C

20070126461 - Data acceleration device and data transmission apparatus using the same: A data acceleration device may include a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a second node... Agent: Marshall, Gerstein & Borun LLP

20070126470 - Apparatus and method for controlling on die termination: An apparatus for controlling an on die termination (ODT) includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a comparing control... Agent: Mcdermott Will & Emery LLP

20070126468 - Device for controlling on die termination: An on die termination (ODT) control device includes a latency block for buffering an ODT control signal to output a latency control signal by selecting one of a plurality of intermediate control signals, which are generated by sequentially delaying the buffered ODT control signal in synchronization with an internal clock,... Agent: Mcdermott Will & Emery LLP

20070126469 - Device for controlling on die termination: An on die termination (ODT) control device includes a mode register set for generating a clock control signal based on mode set information; a clock control unit for receiving an internal clock signal and a delay locked loop (DLL) clock signal and outputting an intermediate internal clock signal and an... Agent: Mcdermott Will & Emery LLP

20070126464 - Dynamic on-die termination launch latency reduction: Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination resistance circuit to provide a termination resistance for the I/O circuit. The integrated... Agent: Intel Corporation C/o Intellevate, LLC

20070126462 - Enabling multiple memory modules for high-speed memory interfaces: In some embodiments a memory module includes a first on-chip termination device and a second on-chip termination device coupled to the first on-chip termination device to obtain an input impedance that is frequency independent. Other embodiments are described and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20070126472 - Line reflection reduction with energy-recovery driver: A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from... Agent: Mcdermott Will & Emery LLP

20070126471 - On die thermal sensor of semiconductor memory device and method thereof: An on die thermal sensor (ODTS) includes a thermal sensor for outputting a first comparing voltage by detecting a temperature of the semiconductor memory device; a comparing unit for outputting a trimming code by comparing the first comparing voltage with a second comparing voltage and increasing or decreasing a preset... Agent: Blakely Sokoloff Taylor & Zafman

20070126463 - Polarity driven dynamic on-die termination: Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further... Agent: Intel Corporation C/o Intellevate, LLC

20070126466 - Semiconductor memory device for adjusting impedance of data output driver: A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the... Agent: Mcdermott, Will & Emery

20070126467 - Test device for on die termination: An on die termination (ODT) test device includes: a control unit for selectively activating a plurality of pull-up signals and a plurality of pull-down signals by performing a logic operation to an ODT control signal for controlling a resistor of a termination terminal, an off chip driver (OCD) control signal... Agent: Blakely Sokoloff Taylor & Zafman

20070126465 - Time multiplexed dynamic on-die termination: Embodiments of the invention are generally directed to systems, methods, and apparatuses for time-multiplexed dynamic on-die termination. In an embodiment, an integrated circuit receives, during a first clock, an on-die termination (ODT) activation signal at its ODT pin. The integrated circuit also receives, during a second clock, an ODT value... Agent: Intel Corporation C/o Intellevate, LLC

20070126473 - Power saving method in an integrated circuit programming and control circuit: A circuit in an integrated circuit having an input terminal to be coupled to a resistor network for selecting one of multiple digital states in the integrated circuit includes a voltage decode circuit, a control circuit and a power-up control circuit. The first input terminal receives an input voltage having... Agent: Patent Law Group LLP

20070126474 - Crossbar switch architecture for multi-processor soc platform: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers... Agent: Ladas & Parry LLP

20070126475 - Method and apparatus for semi-automatic extraction and monitoring of diode ideality in a manufacturing environment: A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070126476 - Semiconductor integrated circuit: A semiconductor integrated circuit includes an external terminal input with an external power supply voltage, a plurality of field effect transistors connected between the external terminal and an internal power supply line and a control circuit input with potentials of spots where voltage drops from output points of the output... Agent: Mcginn Intellectual Property Law Group, PLLC

20070126478 - Method of producing and operating a low power junction field effect transistor: A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET... Agent: Buchanan, Ingersoll & Rooney PC

20070126477 - Output driver for dynamic random access memory: An output driver includes a pre-pull up drive unit configured to perform a pre-pull up drive operation; a pre-pull down drive unit configured to perform a pre-pull down drive operation; a drive unit configured to perform a drive operation in response to outputs of the pre-pull up drive unit and... Agent: Mcdermott Will & Emery LLP

20070126479 - Semiconductor memory device with signal aligning circuit: A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals... Agent: Mcdermott Will & Emery LLP