Electronic digital logic circuitry inventions 05/07

20070120574 - Method and apparatus for can bus auto-termination: A cable area network (CAN) bus termination (100) is provided by an interface 104 operably coupling a cable detection input pin (3), a switch (120) and a termination resistance (130) to detect the presence and absence of one or more cables (108). The termination resistance (130) is automatically enabled to... Agent: Motorola, Inc Intellectual Property Section

20070120575 - Multiple channel modules and bus systems using same: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.... Agent: Hunton & Williams LLP/rambus Inc. Intellectual Property Department

20070120576 - Look-up table action: A first block represents a two or three dimensional object in a Computer Aided Design (CAD) model, and has a visual presentation in a presentation of the CAD model based on a first plurality of property values denoted by a first label in a plurality of labels. User input specifying... Agent: Fish & Richardson P.C.

20070120577 - Semiconductor integrated apparatus using two or more types of power supplies: A semiconductor integrated apparatus includes a control circuit unit which is connected to a low potential power supply terminal and a ground potential power supply terminal, and to which a predetermined low potential power supply output is supplied via the low potential power supply terminal, an output circuit unit which... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070120578 - Integrated header switch with low-leakage pmos and high-leakage nmos transistors: System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal... Agent: Texas Instruments Incorporated

20070120579 - Integrated circuit device and electronic instrument: An integrated circuit device includes a first transfer mode first transmitter circuit including first and second transmission drivers and a second transfer mode second transmitter circuit including third and fourth transmission drivers. A transistor PT1 of the first transmission driver and a transistor PT3 of the third transmission driver are... Agent: Harness, Dickey & Pierce, P.L.C

20070120580 - Non-volatile memory devices and methods of fabricating the same: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and... Agent: Harness, Dickey & Pierce, P.L.C

20070115024 - System monitor in a programmable logic device: Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor includes an analog-to-digital converter which is reconfigurable responsive to input via a dynamic... Agent: Xilinx, Inc Attn: Legal Department

20070115025 - Receiver circuit: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a... Agent: Mcdermott Will & Emery LLP

20070115026 - Load-aware circuit arrangement: The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the drive capacity of the circuit component is adjusted responsive to the determination result. In particular, the circuit component is tailored... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070115027 - Nanotube-based logic driver circuits: Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070115028 - Method and apparatus for protecting a circuit during a hot socket condition: The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital high... Agent: G. Victor Treyz

20070115029 - Circuit element: A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (VDD) and lower voltage level (VSS), in such a way that the paired transistors operate in subthreshold. N input terminals (X1, X2, . . . XN) are connected to the respective paired transistors. Control terminals... Agent: Dennison, Schultz & Macdonald

20070115030 - Differential buffer circuit with reduced output common mode variation: A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs... Agent: Ryan, Mason & Lewis, LLP

20070109012 - Voting scheme for analog signals: A voting scheme for analog signals is described. An analog block is replicated to provide three analog blocks that are designed to have substantially the same analog output based on receiving substantially the same input. Voting is used to compare the analog outputs from the three analog blocks. In one... Agent: Honeywell International Inc.

20070109013 - Method for outputting internal temperature data in semiconductor memory device and circuit of outputting internal temperature data thereby: A method for outputting internal temperature data in a semiconductor memory device can output, at high speed, relatively accurate temperature data externally, without continuously or periodically driving a temperature sensor. The method for outputting the internal temperature data comprises externally outputting internal temperature data stored in a register in a... Agent: Marger Johnson & Mccollom, P.C.

20070109016 - Circuit and method for contact pad isolation: A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse... Agent: Trask Britt, P.C./ Micron Technology

20070109014 - Nanoscale latch-array processing engines: One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be... Agent: Hewlett Packard Company

20070109015 - Switched integrated circuit connection architectures and techniques: Switched integrated circuit connection architectures and techniques are disclosed. An integrated circuit includes connection segments and switching elements operatively coupled to the connection segments. Any of multiple switchable connections to a functional module of the integrated circuit can be established, as needed, by the switching elements through the connection segments.... Agent: Arnold B. Silverman Eckert Seamans Cherin & Mellott, LLC

20070109018 - Intersection ontologies for organizing data: An intersection ontology may comprise a root node, representing an entire data set, and a second “layer” of nodes, groups of which may be used to represent different types of classifications of the data set. The intersection ontology may then contain one or more layers of nodes that may be... Agent: Connolly Bove Lodge & Hutz LLP

20070109017 - Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic... Agent: G. Victor Treyz

20070109019 - High speed transceiver with low power consumption: High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.... Agent: Ivy Y. Mei

20070109020 - High-side transistor driver having positive feedback for improving speed and power saving: A high-side transistor driver including a driver circuit for generating a driving signal to drive a high-side transistor is provided. A floating supply terminal provides a supply voltage to the driver circuit. A floating ground terminal is connected to a source of the high-side transistor. A bootstrap diode is coupled... Agent: J.c. Patents, Inc.

20070109021 - Spatial light modulator with four transistor electrode driver: A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator. The memory cell includes a first PMOS transistor, wherein a source of the first PMOS transistor is coupled to a first supply voltage. The memory cell also includes a first NMOS... Agent: Townsend And Townsend And Crew, LLP

20070109022 - Differential amplifier circuit: A differential amplifier circuit is provided with transfer gates for interrupting input signals to control a timing of supplying the input signals and a timing of starting the differential amplifier circuit.... Agent: Foley And Lardner LLP Suite 500

20070109023 - Distributing clock signals using metamaterial-based waveguides: Various embodiments of the present invention are directed to global interconnects that employ metamaterial-based waveguides to distribute clock signals to IC internal components. In one embodiment of the present invention, a global interconnect includes an electromagnetic radiation source that radiates electromagnetic waves. The global interconnect also includes a metamaterial-based waveguide... Agent: Hewlett Packard Company

20070103185 - Dual path redundancy with stacked transistor voting: A method of operation and an apparatus for radiation hardening a combinational logic circuit are presented. A section of logic that is to be radiation hardened is identified. An entire logic circuit or a portion of the logic circuit may be radiation hardened. Once the section of logic is identified,... Agent: Honeywell International Inc.

20070103187 - Impedance circuit, power supply device: There is disclosed an impedance circuit which realizes negative impedance with ease, and a power supply device having negative output impedance. An impedance circuit 1 connected to an external circuit comprises: a current inverter circuit 11 having an input terminal connected to outside; a passive circuit 10 having an input... Agent: Staas & Halsey LLP

20070103186 - Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection: A circuit design method and transmitter that enables flexible control of amplitude, pre- emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control... Agent: Dillon & Yudell LLP

20070103190 - Semiconductor device with bus terminating function: The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output transistor, which drives an output node in accordance with an internal signal. The area of... Agent: Mcdermott Will & Emery LLP

20070103189 - Semiconductor device, test system and method of testing on die termination circuit: A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a... Agent: Mills & Onello LLP

20070103188 - Semiconductor memory chip with on-die termination function: A semiconductor memory chip with an On-Die Termination (ODT) function is disclosed, which comprises a delay locked loop (DLL) circuit, a synchronous circuit, an asynchronous circuit, a select signal generator, and a selector. The DLL circuit is configured to produce a local clock signal in response to a clock signal... Agent: Mcdermott Will & Emery LLP

20070103191 - Semiconductor-integrated circuit utilizing magnetoresistive effect elements: A semiconductor integrated circuit device able to configure a desired circuit in accordance with a circuit configuration instruction signal given from the outside and able to operate the configured circuit is provided. The semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of... Agent: Rader Fishman & Grauer PLLC

20070103192 - Bit stream compatible fpga to mpga design conversions: A method of converting designs from a field programmable gate array (FPGA) to a mask programmable gate array (MPGA), comprising: an FPGA comprising a programmable logic block array, and a plurality of programmable interconnect wires, and a bit-stream of memory data to program the FPGA; and an MPGA comprising identical... Agent: Raminda U. Madurawe

20070103193 - Configurable circuit with configuration data protection features: A configurable circuit that includes configuration data protection features, and related methods, are described herein.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070103194 - Dual redundant dynamic logic: A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantially the same outputs when receiving substantially the same inputs.... Agent: Honeywell International Inc.

20070103195 - High speed and low power sram macro architecture and method: Circuits and methods are described for reducing leakage power in integrated circuit devices whose logic transistors (e.g., logic circuits, latches, and/or output stages) are powered through one or more controllable source transistors. By way of example the circuit has at least one source transistor (e.g., power, ground, or both power... Agent: John P. O'banion O'banion & Ritchey LLP

20070103196 - Magnetic transistor circuit with the exor function: A magnetic transistor circuit has a first and a second magnetic transistor. These two magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The EXOR logic function of the binary system... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070103197 - Semiconductor device and level conversion circuit: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a... Agent: Mcdermott Will & Emery LLP

20070103198 - Driver circuit, test apparatus and adjusting method: A test apparatus for testing a device under test is provided. The test apparatus includes a test signal generating section for generating a test signal to be provided to the device under test, a driver circuit for providing the test signal to the device under test and a determination section... Agent: Osha Liang L.L.P.

20070103199 - Systems and methods for transmitting signals across integrated circuit chips: Disclosed are on-chip global electrical signaling systems and methods employing differential current-mode sensing having reduced delay and energy dissipation compared to conventional inverter repeaters. The present inventions can be used for point-to-point connections as well as N-to-1 connections.... Agent: Sheppard, Mullin, Richter & Hampton LLP

20070103200 - Buffer circuit and use thereof: A buffer circuit includes a signal input, a first and a second voltage tap and an inverter circuit including an inverter input coupled to the signal input, an output node and a first and a second supply tap. Furthermore, a first element having a diode-type transfer response is provided, which... Agent: Slater & Matsil LLP

20070103201 - Power reducing logic and non-destructive latch circuits and applications: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to... Agent: Blakely Sokoloff Taylor & Zafman

20070103202 - System and method for reducing power-on-transient current magnitude: System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch.... Agent: Texas Instruments Incorporated

20070096770 - Cascaded pass-gate test circuit with interposed split-output drive devices: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.