Electronic digital logic circuitry inventions 04/07

20070090857 - High performance low power multiple-level-switching output drivers: Long existing performance, noise, and power consumption problems of prior art output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. Output drivers of the present invention can be fully compatible with HSTL or SSTL interfaces... Agent: Jeng-jye Shau

20070090858 - Inverter circuit having a feedback switch and methods corresponding thereto: An inverter circuit (500) having a drive transistor (102) that operably couples to a voltage bias input (101) (and where that drive transistor controls the inverter circuit output by opening and closing a connection between the output (105) and ground (104)) is further operably coupled to a feedback switch (401).... Agent: Fitch Even Tabin And Flannery

20070090859 - Signal transmission circuit: A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the... Agent: Mcdermott Will & Emery LLP

20070085560 - Apparatus and method for enabling a multi-processor environment on a bus: The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requires active termination impedance control. The apparatus includes a first... Agent: Huffman Law Group, P.C.

20070085562 - Clock methods and circuits for optimized on-die termination: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing... Agent: Silicon Edge Law Group, LLP

20070085561 - Output circuit for a hub chip for outputting a high-frequency signal, a hub chip, a memory module and a method for operating an output circuit: The invention relates to an output circuit for a hub chip and a method for actuating an output circuit for outputting a high-frequency differential output signal between a first and a second output node, having a differential amplifier unit which comprises a first switching device and a first terminating resistor... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070085565 - Dedicated logic cells employing configurable logic and dedicated logic functions: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two... Agent: Haynes Beffel & Wolfeld LLP

20070085564 - Programmable logic cells with local connections: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers... Agent: Haynes Beffel & Wolfeld LLP

20070085563 - Switch block for fpga architectures: A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.... Agent: Seed Intellectual Property Law Group PLLC

20070085566 - Level shift circuit: A level shift circuit has a driving circuit and an output circuit. The driving circuit has a clamp circuit for receiving first and second bias potentials, outputting first and second drive signals which are not less than a reference potential, less than the first bias potential, and complementary to each... Agent: Mcdermott Will & Emery LLP

20070085567 - Cmos circuit arrangement: A clock transistor and a second operating potential functioning as a circuit breaker, are mounted between the outlet of an NMOS logic circuit.... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070085568 - Peripheral device connection current compensation circuit: A peripheral device connection current compensation circuit is proposed, which is designed for use in conjunction with a peripheral control interface on a computer platform, for the purpose of responding to an event of an external peripheral device being connected to the peripheral control interface by providing a current compensating... Agent: Edwards & Angell, LLP

20070085569 - Magnetic or/nand circuit: A magnetic OR/NAND circuit has a first, a second, a third, and a fourth magnetic transistor. These four magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The ‘OR’ and ‘NAND’... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070080707 - Selective on-die termination for improved power management and thermal distribution: A system, method and device for managing power distribution on a shared bus system that interconnects multiple devices each containing a signal termination component are disclosed herein. In one embodiment, the method of the invention includes detecting and communicating thermal indicia of one or more of the devices in the... Agent: Dillon & Yudell LLP

20070080708 - H-bridge circuit with shoot through current prevention during power-up: The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the high side transistor; pull down devices coupled to a control node of the high side transistor and to a control node of the low side transistor;... Agent: Texas Instruments Incorporated

20070080709 - Integrated circuit communication techniques: An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which drive a pair of adjacent wires with differential current pulses that are received by a differential... Agent: Venable LLP

20070080713 - Circuit architecture for an integrated circuit: An integrated circuit comprising at least one group comprising having multiple arithmetic/logic units arranged in sub-groups. In the sub-groups at inputs of multiple arithmetic/logic units, in each case a single one of the first selection units is connected on the input side, wherein no other selection unit is connected directly... Agent: O'shea, Getz & Kosakowski, P.C.

20070080711 - Dedicated logic cells employing sequential logic and contol logic functions: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two... Agent: Haynes Beffel & Wolfeld LLP

20070080710 - Interconnection resources for programmable logic integrated circuit devices: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070080712 - Semiconductor memory apparatus and method of resetting input/output lines of the same: A semiconductor memory apparatus includes a plurality of unit cell blocks formed in row and column directions, at least a pair of first input and output lines formed at predetermined intervals in the row direction, at least a pair of second input and output lines formed at predetermined intervals in... Agent: Venable LLP

20070080714 - Flip-flop circuit: Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or not the bypass signal is activated. A latch circuit latches input... Agent: Mcdermott Will & Emery LLP

20070080715 - Quad state logic design methods, circuits, and systems: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.... Agent: Texas Instruments Incorporated

20070080716 - Hot plug control apparatus and method: An apparatus for controlling a hot plug bus slot on a bus has an input for receiving a set of float signals (i.e., the set may have one or more float signals), and a driver having an output electrically couplable with the bus. The apparatus also has float logic operatively... Agent: Bromberg & Sunstein LLP

20070080717 - Semiconductor device: A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line. The semiconductor device may include a data transfer unit... Agent: Marshall, Gerstein & Borun LLP

20070080718 - High speed signaling system with adaptive transmit pre-emphasis: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first... Agent: Shemwell Gregory & Courtney LLP

20070080719 - Buffer: A buffer is disclosed. The buffer may include a buffer controller for buffering a refresh signal enabled in an auto-refresh operation synchronously with an external clock signal, a logic circuit for performing a logic operation with respect to an output signal from the buffer controller and a specific signal to... Agent: Marshall, Gerstein & Borun LLP

20070080720 - Semiconductor integrated circuit: The semiconductor integrated circuit includes: a first transistor of a first conductivity type connected between a first power supply and an output node and turned ON according to a first clock to put the output node to a first logic level; a second transistor of a second conductivity type turned... Agent: Mcdermott Will & Emery LLP

20070075729 - Digital programmable phase generator: A programmable phase shifter is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ inverter and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of phase shift and the phase shifter selectively imparts a respective... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070075730 - Data transfer circuit for transferring data between a first circuit block and a second circuit block: A data transfer circuit includes a first transfer circuit receiving the first transfer signal, a second transfer circuit receiving the second transfer signal, a third transfer circuit receiving the first transfer signal and an inverted first transfer signal from the first transfer circuit and transferring the first transfer signal in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070075731 - Method and apparatus for reducing noise in a dynamic manner: An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to... Agent: Ibm Microelectronics Intellectual Property Law

20070075732 - System and method for using dummy cycles to mask operations in a secure microcontroller: A secure device includes a memory capable of storing information. The secure device also includes a secure microcontroller capable of securing the information in the memory. The secure microcontroller includes a plurality of registers. The secure microcontroller also includes combinatorial logic capable of receiving at least one output value provided... Agent: Lisa K. Jorgenson, Esq. Stmicroelectronics, Inc.

20070075733 - Fpga powerup to known functional state: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via... Agent: Hoffman, Warnick & D'alessandro LLC

20070075737 - Configurable circuits, ic's, and systems: Some embodiments of the invention provide configurable integrated circuit (IC) that has a first interface rate for exchanging signals with a circuit outside of the configurable IC. The configurable IC has an array of configurable circuits. The array includes several configurable logic and interconnect circuits. Each configurable logic circuit can... Agent: Stattler, Johansen, And Adeli LLP

20070075739 - Dedicated logic cells employing configurable logic and dedicated logic functions: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two... Agent: Haynes Beffel & Wolfeld LLP

20070075740 - Dedicated logic cells employing configurable logic and dedicated logic functions: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two... Agent: Haynes Beffel & Wolfeld LLP

20070075741 - Dedicated logic cells employing sequential logic and control logic functions: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two... Agent: Haynes Beffel & Wolfeld LLP

20070075736 - Fpga powerup to known functional state: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via... Agent: Hoffman, Warnick & D'alessandro LLC

20070075734 - Reconfigurable network on a chip: An architecture for a reconfigurable network that can be implemented on a semiconductor chip is disclosed, which includes a hierarchical organization of network components and functions that are readily programmable and highly flexible. Essentially, a reconfigurable network on a chip is disclosed, which includes aspects of reconfigurable computing, system on... Agent: Honeywell International Inc.

20070075738 - Semiconductor integrated circuit device: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070075742 - Tileable field-programmable gate array architecture: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals,... Agent: Sierra Patent Group, Ltd.

20070075735 - Xb/yb coder programmed within an embedded array of a programmable logic device: A programmable logic device (PLD) with logic blocks and an embedded array block includes an x-bit (xB)/y-bit (yB) coder programmed into the embedded array block instead of into the logic blocks. An xB/yB coder programmed into an embedded array block of a PLD instead of into logic blocks utilizes less... Agent: Avago Technologies, Ltd.

20070075744 - Circuits having precision voltage clamping levels and method: A slew rate control circuit includes a receiver for receiving input signals and an output generator for generating output signals based on the input signals. The slew rate control circuit also includes an electrical interconnection coupling an output of the receiver and an input of the output generator. In addition,... Agent: Stmicroelectronics, Inc.

20070075745 - Output driver for controlling impedance and intensity of pre-emphasis driver using mode register set: An output driver controls impedance using a mode register set. The output driver includes a main driving circuit that outputs and drives a main signal based on a data signal to a predetermined transmission line, an auxiliary driving circuit that outputs and drives an auxiliary signal to the transmission line,... Agent: Mills & Onello LLP

20070075743 - Semiconductor integrated circuit having current leakage reduction scheme: A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a... Agent: Borden Ladner Gervais LLP

20070075746 - System and method for glitch detection in a secure microcontroller: An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch... Agent: Lisa K. Jorgenson, Esq. Stmicroelectronics, Inc.