Electronic digital logic circuitry inventions 03/07

20070069764 - Apparatus and methods for adjusting performance of integrated circuits: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias... Agent: Law Offices Of Maximilian R. Peterson

20070069765 - Multiple-channel agile high-voltage sequencer: A high-voltage sequencer system includes positive and negative high-voltage supplies. A supply regulator is connected to the positive high-voltage supply. A master sequencer and programmable logic controller is connected to the supply regulator to control operation thereof. A high voltage regulator output circuit is connected to the supply regulator to... Agent: John H. Lynn

20070063728 - Logic cell with two isolated redundant outputs, and corresponding integrated circuit: The disclosure relates to a logic cell for an integrated circuit, including two redundant outputs, a first output equipped with an output transistor of type P and a second output equipped with an output transistor of type N. Such a cell includes isolation element connecting the first and second outputs... Agent: Westman Champlin & Kelly, P.A.

20070063729 - Negative voltage noise-free circuit for multi-functional pad: A circuit and a method are provided to produce a noise-free multi-input I/O pad for an integrated circuit chip. The circuit includes a normal mode internal node, which connects to normal mode circuitry and a test mode internal node, which connects to test mode circuitry. There are separate transfer devices... Agent: Stephen B. Ackerman

20070063730 - Variable impedence output buffer: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the... Agent: Leffert Jay & Polglaze, P.A.

20070063731 - Impedance adjusting circuit and impedance adjusting method: An impedance adjusting circuit for adjusting an impedance of an output buffer of a DDR2 memory, using an OCD impedance adjusting function, from a side of a memory controller, includes first and second terminals, first and second switches, a comparator, and a control circuit. The DDR2 memory has an OCD... Agent: Sughrue Mion, PLLC

20070063732 - Area efficient fractureable logic elements: A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in... Agent: Beyer Weaver & Thomas, LLP Attn: Altera

20070063733 - Programmable logic device architecture for accommodating specialized circuitry: A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized circuitry. The peripheral specialized regions, which are not connected to the remainder of the programmable logic device (and may be made on... Agent: Fish & NeaveIPGroup

20070063735 - Semiconductor integrated circuit device: A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070063734 - Voltage level shifter: Disclosed is a voltage level shifter, including a pull-up circuit, a voltage drop circuit and a pull-down circuit. Through the voltage level shifter, an input voltage is transformed into an output voltage having a different level as compared to that of the input voltage. With the voltage drop circuit, voltages... Agent: Birch Stewart Kolasch & Birch

20070063736 - Soft-start circuit and method for power-up of an amplifier circuit: A method and circuit for providing a soft start-up process for an amplifier circuit to reduce or prevent destructive overshoot of an output voltage are provided. In accordance with an exemplary embodiment of the present invention, an exemplary method and circuit are configured to suitably momentarily replace an actual fixed... Agent: Texas Instruments Incorporated

20070063738 - Cmos logic circuitry: A complimentary metal oxide semiconductor (CMOS) circuit may include a CMOS output stage comprising at least one p-channel metal oxide semiconductor (PMOS) component and at least one n-channel metal oxide semiconductor (NMOS) component connected in series between first and second voltage rails, a juncture between the at least one PMOS... Agent: Hewlett Packard Company

20070063737 - Integrated interface circuitry for integrated vrm power field effect transistors: A down converter includes an interface section, which connects the down converter to switches and respective driver circuits, wherein the driver circuits and the switches are combined on an integrated circuit. The driver circuits include a high-side driver circuit, and a low-side driver circuit. The integration of the driver circuits... Agent: Philips Intellectual Property & Standards

20070063739 - Pre-emphasis apparatus, low voltage differential signaling transmitter including the same and pre-emphasis method: A pre-emphasis apparatus of a LVDS transmitter includes a pre-emphasis signaling generation unit and a pre-emphasis current output unit. The pre-emphasis signal generation unit generates a pre-emphasis pulse signal based on N parallel data signals received from an external source and N-phase clock signals received from a phase locked loop,... Agent: Mills & Onello LLP

20070063740 - Nanotube-based switching elements and logic circuits: Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070057690 - Semiconductor integrated circuit: A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number... Agent: Rader Fishman & Grauer PLLC

20070057691 - Output driver circuit: The present invention relates to an output driver circuit for a semiconductor memory device, in particular, a memory device using a DDR II concept or a concept similar thereto, which can reduce a variation in the slew rate of an output driver thereof between maximum and minimum values, while satisfying... Agent: Marshall, Gerstein & Borun LLP

20070057692 - Driver impedance control apparatus and system: A driver impedance control apparatus and system for determining the impedance of at least one driver are provided. The driver impedance control apparatus includes a first reference impedance, a second reference impedance, a dummy pull-up array, a dummy pull-down array, a pull-up array control unit and a pull-down array control... Agent: Jianq Chyun Intellectual Property Office

20070057693 - Reconfigurable circuit with redundant reconfigurable cluster(s): A reconfigurable circuit having redundant reconfigurable clusters is described herein.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070057694 - Digital cmos-input with n-channel extended drain transistor for high-voltage protection: A circuit and a method are given, to realize an electronic system for combined usage at differing voltage ranges as defined by a low-voltage range for operating standard CMOS devices and a high-voltage range exceeding said standard CMOS low-voltage operating range significantly by multiples and thus necessarily utilizing input ports... Agent: Stephen B Ackerman

20070057696 - Semiconductor integrated circuits with power reduction mechanism: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070057695 - Semiconductor memory chip with re-drive unit for electrical signals: A semiconductor memory chip includes a re-drive unit for re-driving electrical signals to at least one semiconductor memory chip connected thereto. The re-drive unit includes a direct line connection between two connecting nodes, i.e., one input terminal and one output terminal of the semiconductor memory chip.... Agent: Edell, Shapiro & Finnan, LLC

20070052441 - Superconducting circuit for generating pulse signal: A superconducting circuit includes a first transformer to produce a first alternating-current output at a secondary-side inductor, a second transformer to produce a second alternating-current output at a secondary-side inductor, a first pulse generating circuit to produce a single flux quantum pulse responsive to the first alternating-current output, a second... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070052442 - Redundancy circuits hardened against single event upsets: A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block receives a first data input and second... Agent: Honeywell International Inc.

20070052443 - Buffer circuit: A buffer circuit (31), for example a repeater or receiver circuit for a signal wire of an on-chip bus, receives an input signal, and produces an output signal. The buffer circuit (31) comprises a first inverting stage (7) and a second inverter stage (9). The second inverting stage (9) provides... Agent: Philips Intellectual Property & Standards

20070052444 - Programmable interconnect structures: A programmable interconnect structure to couple a first wire segment to a second wire segment of an integrated circuit comprising: a pass-gate to electrically couple the first wire segment to the second wire segment fabricated on a substrate layer, and a configuration circuit including at least one memory element to... Agent: Raminda U. Madurawe

20070052445 - Pre-buffer level shifter and input/output buffer apparatus: A pre-buffer level shifter and an I/O buffer apparatus are provided. The pre-buffer level shifter includes a switchable current source, a current mirror, a buffer unit, a first clamping circuit and a second clamping circuit. Because of a clamping circuit inside a thin oxide MOS transistor device of the pre-buffer... Agent: J C Patents, Inc.

20070052446 - Driver circuit: A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and... Agent: Schwegman, Lundberg, Woessner & Kluth, P.a.

20070052447 - Cmos buffer circuits and integrated circuits using the same: CMOS buffer circuits with reduced short circuit current. In the CMOS buffer circuit, an output stage drives an output terminal and comprises a first output transistor of a first conductive type and a second output transistor of a second conductive type. An output driving unit produces a first signal to... Agent: Birch Stewart Kolasch & Birch

20070052448 - Electronic circuit with a chain of processing elements: A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic circuit (14) of a next processing... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070046323 - Control circuitry for power gating virtual power supply rails at differing voltage potentials: A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20070046324 - Sharing a static random-access memory (sram) table betweeen two or more lookup tables (luts) that are equivalent to each other: In one embodiment, a system for sharing a static random-access memory (SRAM) table between two or more lookup tables (LUTs) that are equivalent to each other includes at least two basic logic elements (BLEs) each associated with a truth table representing a particular function provided by the BLE. The particular... Agent: Baker Botts L.L.P.

20070046325 - System-on-a-chip integrated circuit including dual-function analog and digital inputs: An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture programmably coupling selected ones of the plurality of inputs, the plurality... Agent: Sierra Patent Group, Ltd.

20070046326 - Circuit and circuit connecting method: A network structure configures a blocking network having constraint against such a combination of said network input terminal and network output terminal as to make it unfeasible to further connect, when connecting first network input terminals to first network output terminals, second network input terminals to any one of the... Agent: Arent Fox PLLC

20070046327 - Shift register circuit: A shift register circuit having shift registers comprising a first transistor having a gate and a first source/drain for receiving an output signal of a pre-stage shift register, a second transistor having a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a first... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070046328 - Self-excited inverter circuit: A self-excited inverter circuit, includes: a booster transformer with a secondary coil, a feedback coil, and a primary coil respectively wound thereon, the primary coil including a center tap to which operating power can be supplied; a first N-channel FET having a drain to which is connected one terminal of... Agent: Osha Liang L.L.P.

20070046330 - Cmos circuits with reduced crowbar current: Various circuit embodiments comprise an input node to receive an input signal for a CMOS transistor stack, a first output node to deliver the input signal to a PMOS pull-up transistor of the CMOS transistor stack, and a second output node to deliver the input signal to an NMOS pull-down... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070046329 - Differential duty cycle restoration: Embodiments of the invention provide methods and apparatuses for restoring a duty cycle of a complementary output signal pair. In one embodiment, the output signal pair is brought in phase with a complementary input signal pair by delaying a complementary intermediate signal pair from which the output signal pair is... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070046333 - Differential output circuit with stable duty: A differential output circuit includes a bias circuit connected with a first voltage. An input circuit section includes first and second MOS transistors of a first conductive type, and the first and second MOS transistors are connected with the first voltage through the bias circuit, and gates of the first... Agent: Foley And Lardner LLP Suite 500

20070046332 - Output buffer circuit: Disclosed is an output buffer including a first output buffer for data for receiving a data signal and outputting an output signal from an output terminal, a second output buffer with an output end thereof connected to the output terminal, and a selection circuit. The selection circuit receives a control... Agent: Mcginn Intellectual Property Law Group, PLLC

20070046331 - Output driver robust to data dependent noise: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which... Agent: Fletcher Yoder

20070046334 - Universal single-ended parallel bus: A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal... Agent: Garlick Harrison & Markison

20070046335 - Programmable driver delay: Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20070046336 - Thin film transistor array substrate: A thin film transistor array substrate comprises thin film transistors and pixel electrodes formed at respective pixels that are defined by gate lines and data lines that orthogonally intersect each other. The thin film transistor array substrate further comprises a plurality of gate pad units that group a plurality of... Agent: Brinks Hofer Gilson & Lione