Electronic digital logic circuitry inventions 02/07

20070040574 - Apparatus and method for independent control of on-die termination for output buffers of a memory device: An apparatus and method providing independent control of on-die termination (ODT) of output buffers. The ODTs for the buffer circuits of an input/output (I/O) buffer can be enabled and disabled in response to an ODT control signal. Additionally, the ODTs for a first set of the buffer circuits can be... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070040573 - Output impedance calibration circuit with multiple output driver models: A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the output drivers and used to... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070040575 - Integrated circuits with reduced leakage current: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled... Agent: Macpherson Kwok Chen & Heid LLP

20070040576 - Apparatus and methods for power management in integrated circuits: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.... Agent: O'keefe, Egan & Peterman, L.L.P. Building C, Suite 200

20070040577 - Apparatus and methods for optimizing the performance of programmable logic devices: A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least... Agent: Law Offices Of Maximilian R. Peterson

20070040578 - Input/output interface with current sensing: An interface circuit includes an input terminal, a controlled current sink, a current measurement arrangement, and a logic circuit. The input terminal is configured to receive an input signal. The controlled current sink is operably coupled to the input terminal, and is operable to controllably take up a current from... Agent: Maginot, Moore & Beck Chase Tower

20070040579 - Swing limiter: A swing limiter comprises: a logic circuit including at least one first pull-up transistor and at least one first pull-down transistor which are serially connected between a first node and a second node and receive at least one input signal to generate an output signal, respectively; a second pull-up transistor... Agent: Mills & Onello LLP

20070040580 - Reference buffer with improved drift: A reference voltage circuit having an open-loop buffer driven by a matching buffer included within a closed-loop, generates a stable differential or single-ended voltage while minimizing signal-dependent short-term and long-term drift. The open-loop buffer may be a replica of the closed-loop buffer, reducing the effect of a signal coupled on... Agent: Texas Instruments Incorporated

20070040581 - Word line driver with reduced leakage current: A circuit system having a first inverter, a second inverter and a blockage module is disclosed. The first inverter is coupled between a supply voltage and a complementary input signal, for generating a first output signal on an output terminal thereof in response to an input signal received by an... Agent: Howard Chen, Preston Gates & Ellis LLP

20070040582 - Inferential power monitor without voltage/current transducers: A system that facilitates estimating power consumption in a computer system by inferring the power consumption from instrumentation signals. During operation, the system monitors instrumentation signals within the computer system, wherein the instrumentation signals do not include corresponding current and voltage signals that can be used to directly compute power... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070040583 - Semiconductor device: The semiconductor device of the present invention includes a bootstrap circuit, the bootstrap circuit including: a selection transistor composed of an n-channel MOS transistor; a booster transistor of which a gate is connected to a drain of the selection transistor; and a boosting circuit that is connected between the gate... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070040584 - Dual-gate dynamic logic circuit with pre-charge keeper: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20070040585 - High speed, low power cmos logic gate: A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low threshold voltage devices in the evaluation stage, yet uses higher threshold voltage devices in other portions of the gate... Agent: Dickstein Shapiro LLP

20070035326 - Memory chip and method for operating a memory chip: Methods and apparatus for setting various terminations of a memory chip. In one embodiment, the memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070035328 - Configurable logic element with expander structures: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits... Agent: Xilinx, Inc Attn: Legal Department

20070035327 - Fast method for functional mapping to incomplete lut pairs: A configuration for a programmable device is determined to implement an incomplete function using at least two logic cells. Function inputs are partitioned into portions associated with first and second logic cells. The partitioning is screened to determine if it is potentially acceptable by determining if a portion of the... Agent: Townsend And Townsend And Crew LLP/ 015114

20070035329 - Look-up table based logic macro-cells: A programmable look up table (LUT) structure of an integrated circuit, comprising: two or more LUT circuits, each said LUT circuit comprising: one or more inputs; and a plurality of LUT values; and at least one output; and a configurable multiplexer (MUX) circuit comprising: a plurality of inputs; and one... Agent: Raminda U Madurawe

20070035330 - Columnar floorplan: An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column... Agent: Xilinx, Inc Attn: Legal Department

20070035331 - Scan friendly domino exit and domino entry sequential circuits: A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the... Agent: Lee & Hayes, PLLC C/o Portfolioip

20070035332 - Circuit and method for calculating a logical combination of two input operands: A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal... Agent: Dickstein Shapiro LLP

20070030024 - Memory system including on-die termination unit having inductor: Provided is a memory system with an inductor. In the memory system, the inductor is connected to an on-die termination unit of a memory chip, thereby realizing constant gain characteristics without respect to a variation in an operating frequency. The inductor of the on-die termination unit may be embodied by... Agent: Harness, Dickey & Pierce, P.L.C

20070030025 - Semiconductor memory device including on die termination circuit and on die termination method thereof: A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during... Agent: Mills & Onello LLP

20070030026 - Multiple-time programming apparatus and method using one-time programming element: A multiple-time programming apparatus and method using one-time programming (OTP) elements are provided. The apparatus comprises a first adjusting OTP element, a second adjusting OTP element and a calculation device. An adjusting data is written into the first adjusting OTP element. When a modification in an IC is desired, the... Agent: Jianq Chyun Intellectual Property Office

20070030028 - Programmable array logic circuit employing non-volatile ferromagnetic memory cells: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no... Agent: Morgan Lewis & Bockius LLP

20070030027 - Programmable interconnect structures: A layout of a programmable interconnect structure, comprising: an active region; and an even plurality of gate regions dividing the active region into a plurality of active stripes, said active stripes arranged into disjoint first, second and third sets; and a plurality of interconnect wires, each interconnect wire coupled to... Agent: Raminda U. Madurawe

20070030029 - Interconnection and input/output resources for programmable logic integrated circuit devices: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from,... Agent: Fish & NeaveIPGroup

20070030030 - Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals: A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous... Agent: Jones Day

20070030031 - Circuit and method for calculating a logic combination of two encrypted input operands: Circuit for calculating a logic combination of two encrypted input operands receivese first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge... Agent: Dickstein Shapiro LLP

20070030032 - Fault tolerant nand gate circuit: A fault tolerant NAND gate circuit includes at least four parallel PMOS transistor and a pair of two serial NMOS transistor. The sources of two NMOS transistor among the four NMOS transistor are coupled to the output of the claimed NAND gate circuit. The claimed fault tolerant NAND gate circuit... Agent: North America Intellectual Property Corporation

20070024316 - Circuit personalization: A method distributes personalized circuits to one or more parties. The method distributes a generic circuit to each party, encrypts a unique personalization value using a secret encryption key, and transmits each encrypted personalization value to the corresponding party. Each party then stores the encrypted personalization value in their circuit.... Agent: Seed Intellectual Property Law Group PLLC

20070024317 - Apparatus for obtaining precision integrated resistors: Integrated circuits with on-chip impedance matching techniques, which can be implemented to provide high precision and which greatly increase the precision of resistors integrated into the integrated circuit, are provided.... Agent: Avago Technologies, Ltd.

20070024318 - Automatic extension of clock gating technique to fine-grained power gating: A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The... Agent: Macpherson Kwok Chen & Heid LLP

20070024319 - Configurable logic circuit arangement: A configurable logic circuit arrangement includes at least one multiplexer for switching logic signals. The multiplexer includes one or more data inputs and one or more control signal inputs. The at least one multiplexer (8, 12, 13) can be configured by one or more external control signal transmitter elements of... Agent: Young & Thompson

20070024320 - Multi-standard transmitter: A multi-standard transmitter includes a differential stage that includes a current generator transistor; first and second transistors connected between a first node and the generator transistor and having respective control terminals connected to a first input terminal, the first and second transistors being interconnected at a first output terminal; third... Agent: Seed Intellectual Property Law Group PLLC

20070024321 - Semiconductor cmos transistors and method of manufacturing the same: A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped source/drain implanted into the semiconductor... Agent: North America Intellectual Property Corporation

20070024322 - Leakage current reduction scheme for domino circuits: A method and system for leakage current reduction in domino circuits is described. The system includes a domino circuit with a dynamic gate, a static gate, and a standby signal to set the domino circuit to an evaluate phase during an inactive mode. The inputs to the static gate are... Agent: Blakely Sokoloff Taylor & Zafman