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Electronic digital logic circuitry January USPTO class patent listing 01/07Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/25/2007 > 14 patent applications in 9 patent subcategories. USPTO class patent listing
20070018682 - Method and apparatus for calibrating driver impedance: The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes providing a signal from a synchronous circuit that is indicative of an impedance mismatch between a driver circuit and a load. The method also includes selecting one... Agent: Williams, Morgan & Amerson
20070018681 - Pin electronics driver: Circuitry for driving a pin includes a first resistive circuit connected to the pin, a first transistor circuit to connect the first resistive circuit to a logic level voltage in response to a trigger voltage, the first transistor circuit and the first resistive circuit together defining a termination impedance, and... Agent: Fish & Richardson P.C.
20070018683 - Signal transmitting device suited to fast signal transmission: A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission... Agent: Antonelli, Terry, Stout & Kraus, LLP
20070018684 - Temperature-compensated output buffer: A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor. The supplemental pull-up circuit is configured to generate... Agent: Trask Britt
20070018686 - Low voltage differential signal receiver and methods of calibrating a termination resistance of a low voltage differential signal receiver: A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based... Agent: Myers Bigel Sibley & Sajovec
20070018685 - Multi-stage light emitting diode driver circuit: A multi-stage light emitting diode (LED) driver circuit is provided. The circuit includes a driver transistor coupled to an LED. The LED is coupled at a drain of the driver transistor and the driver transistor drives current to the LED. A first transistor stack is coupled between a gate of... Agent: Avago Technologies, Ltd.
20070018687 - Line driver with reduced interference: A bus communication system contains a pair of communication conductors and a driver. The driver contains a plurality of pairs of controlled current source circuit, each pair comprising current source circuits of a first and second, mutually opposite polarity, and a control circuit for matching currents drawn by the current... Agent: Philips Intellectual Property & Standards
20070018688 - Digital logic unit: The invention provides a digital logic driven by a master clock signal and includes logic circuitry with processing stages capable of performing logic operations within a fraction of the period of the master clock signal. Furthermore, the digital logic unit comprises clock distribution means that supple clock signals to the... Agent: Texas Instruments Incorporated
20070018689 - High performance clock-powered logic: High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer is used to drive the signal line. The receiving end of the line is connected to a jam latch, preferably followed by an n-latch, followed... Agent: Mcdermott, Will & Emery (los Angeles Office)
20070018690 - Maskable dynamic logic: An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for unmasked bits from... Agent: Robert R. Williams IBM Corporation
20070018691 - Multi-pad structure for semiconductor device: A pad layout structure may include a pad and adjacent circuit areas having an electrostatic protection circuit and a data input/output circuit. The pad may be selectively connected to the adjacent circuit areas depending on the intended use of the pad.... Agent: Marger Johnson & Mccollom, P.C.
20070018692 - Scl type fpga with multi-threshold transistors and method for forming same: A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No.... Agent: Sawyer Law Group LLP
20070018693 - Cml circuit devices having improved headroom: A CML digital circuit includes a load coupled between a power supply node and at least one output node and a logic circuit component coupled to the output node. The logic circuit component has at least one data input node. The logic circuit component comprises a first circuit module and... Agent: Duane Morris, LLPIPDepartment
20070018694 - High-speed cml circuit design: A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output... Agent: Duane Morris, LLPIPDepartment01/18/2007 > 4 patent applications in 4 patent subcategories. USPTO class patent listing
20070013410 - Integrated receiver circuit: An integrated receiver circuit for amplifying an input signal based on a reference signal includes two voltage converters to respectively convert the input and reference signals to level-converted input and reference signals. An amplifier stage includes a PMOS input differential amplifier driven by the converted input and reference signals, and... Agent: Edell, Shapiro & Finnan, LLC
20070013411 - Apparatus and methods for programmable slew rate control in transmitter circuits: High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the... Agent: Fish & NeaveIPGroup
20070013412 - Semiconductor device having super junction structure and method for manufacturing the same: A semiconductor device includes: a cell region; a terminal region; a lower semiconductor layer; a intermediate semiconductor layer on the lower semiconductor layer including a super junction structure; a terminal upper semiconductor layer on the intermediate semiconductor layer; a terminal contact semiconductor region on a surface portion of the terminal... Agent: Posz Law Group, PLC
20070013413 - High-density logic techniques with reduced-stack multi-gate field effect transistors: Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can... Agent: Ryan, Mason & Lewis, LLP01/11/2007 > 4 patent applications in 4 patent subcategories. USPTO class patent listing
20070007991 - I/o circuitry for reducing ground bounce and vcc sag in integrated circuit devices: Methods and circuitry for reducing ground bounce and VCC sag effects in integrated circuit (“IC”) devices is provided. In particular, a via-programmable design for I/O circuitry in IC devices is provided. The via-programmable I/O circuitry is used to disconnect I/O pin driver circuitry from and create a substantially direct connection... Agent: Fish & NeaveIPGroup
20070007993 - High speed integrated circuit: A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a... Agent: Innovation Management Sciences
20070007994 - Interface circuit with a terminator and an integrated circuit and an electronic equipment having the same: Provided is an interface circuit having a terminator, in which the terminator includes parallel-connected first to an Nth resistance elements, where N is an integral number equal to or more than 2, and a first to an nth cut-off elements connected in serial with each of the corresponding n(1≦n<N) first... Agent: Oliff & Berridge, PLC
20070007992 - Method to calibrate dram ron and odt values over pvt: An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use... Agent: Marger Johnson & Mccollom, P.C.
20070007995 - Physical layers: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A... Agent: Blakely Sokoloff Taylor & Zafman
20070007996 - A method and apparatus for reducing leakage in integrated circuits: An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization... Agent: Smith Hopen, Pa
20070007997 - Charge recycling power gate: A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power... Agent: F. Chau & Associates, LLC
20070007998 - System and method for configuring a field programmable gate array: A mechanism within an electronic system for adapting a field programmable gate array (FPGA) to a flash memory device that supports a synchronous serial peripheral interface (SPI) by coupling a small amount of MSI logic with the FPGA and the flash memory device, to configure the FPGA to a designed... Agent: West & Associates, A PC
20070007999 - Systems and methods for programming floating-gate transistors: A floating-gate transistor array and method for programming the same. The floating-gate transistor array includes a plurality of transistors having a source, drain, and floating-gate, whereby the plurality of transistors is arranged into multiple rows and columns. Each row of transistors includes a row programming switch having an output connected... Agent: Troutman Sanders LLP
20070008000 - Passgate structures for use in low-voltage applications: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the... Agent: Fish & NeaveIPGroup
20070008001 - Cascadable level shifter cell: A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to... Agent: The Law Offices Of Gary R. Stanford
20070008002 - High-speed differential receiver: A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level... Agent: Ibm Corporation RochesterIPLaw Dept 917
20070008003 - Self-biased high speed level shifter circuit: A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20070008004 - Apparatus and methods for low-power routing circuitry in programmable logic devices: An interconnect circuit includes a driver circuit and a receiver circuit. The receiver circuit couples to the driver circuit. The driver circuit is configured to receive an input signal and to derive from the input signal a limited swing driver output signal. The receiver circuit is configured to derive from... Agent: Law Offices Of Maximilian R. Peterson
20070008005 - Integrated circuit device including interface circuit and electronic apparatus: An integrated circuit device, includes: an input pad region including a differential signal input region receiving a pair of differential signals, a first power supply input region and a second power supply input region; and an interface circuit including a receiving circuit receiving the pair of differential signals that are... Agent: Harness, Dickey & Pierce, P.L.C
20070008007 - Input/output circuit device: An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a first power supply terminal, and the other of the first source and drain of... Agent: Panasonic Patent Center C/o Mcdermott Will & Emery LLP
20070008006 - Output driver in semiconductor device: There is provided an output driver of a semiconductor device in which a slew rate variance is small despite an environmental change and a slew rate can be easily controlled. The output driver includes a main driver for driving an output terminal, a delay unit for controlling a delay time... Agent: Blakely Sokoloff Taylor & Zafman
20070008008 - Data output device and method of semiconductor device: A data output device is disclosed having a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second... Agent: Marshall, Gerstein & Borun LLP
20070008009 - Source driver for controlling a slew rate and a method for controlling the slew rate: A source driver for controlling a slew rate of a liquid crystal display (LCD) and a method for controlling the slew rate is provided. The source driver includes a plurality of output buffers for driving data lines, and a bias circuit for varying a bias voltage inputted to the output... Agent: F. Chau & Associates, LLC
20070008010 - High voltage integrated circuit driver with a high voltage pmos bootstrap diode emulator: A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is... Agent: Sidley Austin Brown & Wood LLP
20070008011 - Distributed power and clock management in a computerized system: A computer circuit includes a plurality of digital logic circuits, each having a locally regulated voltage supply and a clock. The clock and locally regulated voltage supply of each of the plurality of digital logic circuits are operable to vary under control of a common power controller. A synchronizer coupled... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20070008012 - Scannable dynamic circuit latch: A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate series latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a fast scannable delay reset Domino dynamic latch. A fast... Agent: Wagner, Murabito & Hao LLP
20070008013 - Universal programmable logic gate and routing method: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that... Agent: Alessandro Steinfi, Esq. C/o Ladas & Parry
20070008014 - Layout area efficient, high speed, dynamic multi-input exclusive or (xor) and exclusive nor (xnor) logic gate circuit designs for integrated circuit devices: A layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit design of especial utility with respect to integrated circuit devices. The logic gate design disclosed herein utilizes fewer transistors than traditional static designs and, therefore, requires a smaller amount of integrated circuit... Agent: Hogan & Hartson LLP01/04/2007 > 4 patent applications in 4 patent subcategories. USPTO class patent listing
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