Electronic digital logic circuitry inventions 12/06

20060290375 - High speed integrated circuit: A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a... Agent: Innovation Management Sciences

20060290376 - High speed integrated circuit: A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a... Agent: Innovation Management Sciences

20060290377 - Capacitively coupled pulsed signaling bus interface: A fully alternating current (AC) coupled multi-point, multi-drop or point-to-point bus interconnect uses a low power synchronous pulsed signaling scheme for board-level chip-to-chip communication. A single-ended or differential pulsed signaling transceiver generates a diamond data eye with a small time constant in the pulsed signal. The transceiver includes a high-pass... Agent: Gates & Cooper LLP Howard Hughes Center

20060290378 - Estimation of average-case activity for digital state machines: A method for estimating the average-case activity in a digital circuit includes the steps of identifying a state machine in the digital circuit, and propagating activity values through the state machine to obtain activity information at an output of a flop in the state machine using a predetermined formula.... Agent: Townsend And Townsend And Crew, LLP

20060290379 - Leakage balancing transistor for jitter reduction in cml to cmos converters: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential... Agent: Texas Instruments Incorporated

20060290380 - Semiconductor device: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot... Agent: Fish & Richardson P.C.

20060290381 - A bi-directional bus buffer: A bi-directional bus buffer for applications using the I2C and SMBus, or other bus systems operating on similar principles, able to extend the bus load limit by buffering both the SCL and SDA (clock and data) lines, allowing capacitive loads of up to the limit of 400 pF on both... Agent: Akerman Senterfitt

20060290383 - Dual gate dynamic logic: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20060290385 - Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock: A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20060290384 - Independent gate control logic circuitry: A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20060290382 - Method and apparatus for power consumption reduction in a limited-switch dynamic logic (lsdl) circuit: A method and apparatus for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20060290386 - Nand gate, a nor gate, and output buffer and method thereof: A NAND gate, a NOR gate, an output buffer and method thereof. An example embodiment of the present invention is directed to a NAND gate, including a first transistor having a source to which a supply voltage is applied and a gate to which a ground voltage is applied, a... Agent: Harness, Dickey & Pierce, P.L.C

20060284648 - Method and system for a circuit for timing sensitive applications: Systems and methods for circuits with substantially equal propagation delay while providing different drive strengths are disclosed. These systems and methods may allow for a circuit with a drive strength that is some ratio of an arbitrary strength full drive strength circuit. Additionally, these circuits may have substantially the same... Agent: SprinkleIPLaw Group

20060284649 - Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply... Agent: Vedder Price Kaufman & Kammholz

20060284650 - Logic circuit and semiconductor integrated circuit: The invention provides a logic circuit to identify time difference between signals having a variation in delay, and an integrated circuit which can evaluate variations in delay among internal signals. By using a logic circuit which outputs different number of pulse depending on a relationship of delay when a first... Agent: Eric Robinson

20060279325 - Input circuit for mode setting: An input circuit for mode setting, comprising: a chip selection terminal that is operable both in first and second operation modes; a mode setting terminal that is used to select an operation mode from between the first and second operation modes; a logic holding circuit that holds a logic status... Agent: Nixon Peabody, LLP

20060279324 - Mask-programmable logic device with programmable input/output ports: A mask-programmable logic device includes a macrocell having an external input/output port for “place-and-route” programming by addition of metallization layers. A programmable “fixed” layer allows the external input/output port to be isolated from the remainder of the macrocell so that it “floats,” allowing signals to be routed through the external... Agent: Fish & NeaveIPGroup

20060279326 - Method of interconnect for multi-slot metal-mask programmable relocatable function placed in an i/o region: A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function... Agent: Lsi Logic Corporation

20060279327 - Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an fpga: A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed... Agent: Sierra Patent Group, Ltd.

20060279329 - Mask-programmable logic macro and method for programming a logic macro: A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series... Agent: Maginot, Moore & Beck Chase Tower

20060279328 - Programmable logic circuit and method of using same: A programmable logic circuit, including programmable memory element, suitable for microprocessor applications, and a method of using the circuit are disclosed. The programmable circuit includes at least one logic cell, columns and rows of wires coupled to the logic cell, and a programmable memory element located at the intersection of... Agent: Snell & Wilmer

20060279330 - Methods and apparatus for programmably powering down structured application-specific integrated circuits: Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.... Agent: Fish & NeaveIPGroup

20060279331 - Tri-state output logic with zero quiescent current by one input control: A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in... Agent: Birch Stewart Kolasch & Birch

20060279332 - Voltage-level shifter: In a voltage-level shifter, an input line is configured to convey an input voltage to be shifted. A pair of transistors is coupled to and is configured to receive the input voltage from the input line. There is a first side and a second side, with each side comprising the... Agent: Sawyer Law Group LLP

20060279333 - Apparatus and methods for multi-gate silicon-on-insulator transistors: An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set a gate bias of one gate of the one or more multi-gate transistors... Agent: Law Offices Of Maximilian R. Peterson

20060279334 - Single supply level converter: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20060279335 - Phase interpolator driver: A driver circuit in a phase interpolator is provided. In some embodiments, it comprises an input to receive an input clock signal, an output; and at least one pull-up and pull-down device coupled between the input and output to provide at the output the input clock signal driven at a... Agent: Blakely Sokoloff Taylor & Zafman

20060279336 - Logic processing apparatus, semiconductor device and logic circuit: A logic processing circuit including a plurality of flip-flop including a front stage flip-flop and a rear stage flip-flop, a logic gate circuit network adapted to process data stored in the front stage flip-flop, a result of the process being stored in the rear stage flip-flop, and switching means for... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060279337 - Circuit for providing a logic gate function and a latch function: The invention relates to an electronic circuit comprising differential signal input means, a combining stage, a discriminating stage and differential signal output means. The discriminating stage comprises four transistors (Q8, Q9, Q10, Q11) each having first electrodes (83, 93, 103, 113) and second electrodes (81, 91, 101, 111) and a... Agent: Philips Intellectual Property & Standards

20060273819 - Antibiotic tetrahydro-beta-carboline derivatives: Disclosed are tetrahydro-β-carboline derivatives such as structural formula I, pharmaceutical compositions comprising them and methods of treating bacterial infections. The disclosed compounds are inhibitors of PPAT (phosphopantetheine adenyl transferase), and are useful in the treatment and prevention of diseases caused by bacteria, particularly bacteria dependent on PPAT, for example, species... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20060273820 - Input and output circuit an integrated circuit and method for testing the same: An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the protective circuit; and an additional circuit including a... Agent: Edell, Shapiro & Finnan, LLC

20060273821 - System and method for creating a standard cell library for reduced leakage and improved performance: The present invention provides a system and method for providing a standard cell library for reduced leakage and improved performance. The standard cell library comprises at least two sets of threshold voltage cells. At least one of the sets includes non-mixed threshold voltage cells. At least one of the sets... Agent: Sawyer Law Group LLP

20060273822 - Semiconductor circuit: A semiconductor circuit which includes one or plural fuse circuits being disconnectable and having a connected or disconnected state and a control circuit controlling a controlled circuit is provided. The control circuit controls the controlled circuit according to the state of the fuse circuit or the states of the fuse... Agent: Arent Fox PLLC

20060273823 - Circuit arrangement for supplying configuration data in fpga devices: A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output... Agent: Maginot, Moore & Beck Chase Tower

20060273824 - High current switching circuit for a motor drive three phase inverter for mobile equipment: A power switching assembly includes a circuit board mounted on an insulating substrate, a power switching transistor having a mounting surface mounted to the circuit board and a top surface located opposite the mounting surface, and a heat sink associated with the top surface of the power switching transistor, the... Agent: Zarley Law Firm P.L.C

20060273825 - Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20060273826 - Heat dissipation system: A heat dissipation system includes at least one fan, at least two controllers, a signal generator, and a signal converter. The controllers are electrically connected to the fan and generate an enable signal according to a feedback signal of the fan. The signal generator is electrically connected to the controllers... Agent: Birch Stewart Kolasch & Birch