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Electronic digital logic circuitry September class, title,number 09/06

20060208758 - Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same: A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mode trigger signal on an output. In response to the...

20060208759 - Level shifter: In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors...

20060208760 - Low leakage monotonic cmos logic: A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein...

20060208761 - Semiconductor circuit: A band gap reference circuit is configured by connecting an emitter of a transistor, having the base and the collector thereof grounded, to an internal circuit, and by connecting an emitter of another transistor, having the base and the collector thereof grounded, to the internal circuit via a resistor having...

20060208762 - Data input buffer in semiconductor device: The present invention provides an input buffer for use in a semiconductor device reducing a current consumption and maintaining a reliable operation speed by detecting a level of the reference voltage. The input buffer includes a comparator, having a first biasing device controlled by a buffer enable signal, for sensing...

20060208763 - Controlled load limited switch dynamic logic circuitry: An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic...

20060208764 - Graphics controller integrated circuit without memory interface: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video...

20060202711 - Semiconductor device with bus terminating function: The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output transistor, which drives an output node in accordance with an internal signal. The area of...

20060202710 - Transmission line termination impedance compensation circuit: An on-chip termination impedance compensation circuit is provided. The termination impedance generated by the compensation circuit is precise and could absorb the impedance variances resulted from chip manufacturing process, temperature, and noise. The most significant feature of the compensation circuit is that the termination impedance is provided by a digitally...

20060202714 - Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices: A PLD includes at least one IP block or circuit, and at least one I/O block or circuit. The performance of the at least one IP block is adjusted in order to meet at least one performance characteristic by changing a supply level of the at least one IP block,...

20060202713 - Apparatus and methods for adjusting performance characteristics of circuitry in programmable logic devices: A programmable logic device (PLD) includes at least one general PLD circuit and at least one intellectual property (IP) block or circuit. The PLD further includes a power management circuit. The power management circuit is configured to control power to the PLD circuit and to the IP block....

20060202712 - Automatic resource assignment in stacked module devices: A stacked module device and corresponding module and method are provided where at least some modules have input ports connected to receive first resource related signals and output ports connected to provide second resource related signals. The first and second signals are different, and each module comprises a resource signal...

20060202715 - Re-configurable circuit and configuration switching method: The present invention is a re-configurable circuit capable of reducing latency by selecting a route for skipping the FF of an operation unit and outputting data to a connection destination operation unit if an accumulated process time is below an operation cycle allocated to the operation unit. The operation unit...

20060202717 - Architecture and interconnect scheme for programmable logic circuits: An architecture having a distributed and replicated hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is composed of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability between cells and accessibility to a hierarchical routing...

20060202716 - Method and apparatus for universal program controlled bus architecture: An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated...

20060202718 - Xor circuit: An XOR circuit designed in dual rail includes four shunt transistors, wherein the shunt transistors are disposed to couple an input potential at a first input or a second input with an output....

20060202719 - Semiconductor integrated circuit device and design method thereof: In a semiconductor integrated circuit device in which dynamic type logic circuit cells, in which transistors constituting a logic section are in an unconnected condition, are arranged in two-dimensional array form and wiring for distributing a clock signal to each row of these dynamic type logic circuit cells is provided,...

20060197549 - Chip to chip interface including assymetrical transmission impedances: A chip to chip interface that includes a signal path and a first circuit. The first circuit includes asymmetrical transmission impedances to transmit high signals via the signal path using a first transmission impedance and low signals via the signal path using a second transmission impedance. The first transmission impedance...

20060197550 - Adjusting driver stage output impedance: In order to generate a control signal for adjusting a driver stage with an adjustable output impedance, an impedance signal is generated for a measure of the output impedance of the driver stage. The difference between the impedance signal and a reference signal is calculated, and passed to a sigma-delta...

20060197551 - Adjustment of termination resistance in an on-die termination circuit: The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON...

20060197552 - Mask-programmable logic device with programmable portions: A mask-programmable logic device includes some circuitry that is electrically programmable as in conventional programmable logic devices. This allows a user to adjust certain characteristics of programmed devices whose logic functions have been proven and need not change, but which operate in an environment that changes, necessitating different characteristics, without...

20060197553 - Integrated semiconductor memory with clock-synchronous access control: An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied...

20060197554 - Level shift circuit and shift register and display device: A level shift circuit, a shift register, and a display device in which circuit operation is resistant to influence of variations in characteristics of elements such as transistors. The level shift circuit, includes a first switch turning on or off in accordance with a voltage of a first node, switching...

20060197555 - Input/output circuit and input/output device: An input/output circuit has an output terminal, a first transistor, a second transistor, a pulse generator, and a bias circuit. The first transistor drives the output terminal based on a predetermined signal. The second transistor controls a potential of the gate of the first transistor. The pulse generator outputs a...

20060197556 - Output driver in semiconductor device: An output driver of a semiconductor device, removing the inter-symbol interference noise in data transmission in order to achieve a signal integrity, includes a main driver for driving an output terminal and a supporting driver for controlling the inter-symbol interference noise. The supporting driver is provided with a pull up...

20060197557 - Self dc-bias high frequency logic gate, high frequency nand gate and high frequency nor gate: A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupled to an impedance matching network. The impedance...

20060197549 - Chip to chip interface including assymetrical transmission impedances: A chip to chip interface that includes a signal path and a first circuit. The first circuit includes asymmetrical transmission impedances to transmit high signals via the signal path using a first transmission impedance and low signals via the signal path using a second transmission impedance. The first transmission impedance...

20060197550 - Adjusting driver stage output impedance: In order to generate a control signal for adjusting a driver stage with an adjustable output impedance, an impedance signal is generated for a measure of the output impedance of the driver stage. The difference between the impedance signal and a reference signal is calculated, and passed to a sigma-delta...

20060197551 - Adjustment of termination resistance in an on-die termination circuit: The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON...

20060197552 - Mask-programmable logic device with programmable portions: A mask-programmable logic device includes some circuitry that is electrically programmable as in conventional programmable logic devices. This allows a user to adjust certain characteristics of programmed devices whose logic functions have been proven and need not change, but which operate in an environment that changes, necessitating different characteristics, without...

20060197553 - Integrated semiconductor memory with clock-synchronous access control: An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied...

20060197554 - Level shift circuit and shift register and display device: A level shift circuit, a shift register, and a display device in which circuit operation is resistant to influence of variations in characteristics of elements such as transistors. The level shift circuit, includes a first switch turning on or off in accordance with a voltage of a first node, switching...

20060197555 - Input/output circuit and input/output device: An input/output circuit has an output terminal, a first transistor, a second transistor, a pulse generator, and a bias circuit. The first transistor drives the output terminal based on a predetermined signal. The second transistor controls a potential of the gate of the first transistor. The pulse generator outputs a...

20060197556 - Output driver in semiconductor device: An output driver of a semiconductor device, removing the inter-symbol interference noise in data transmission in order to achieve a signal integrity, includes a main driver for driving an output terminal and a supporting driver for controlling the inter-symbol interference noise. The supporting driver is provided with a pull up...

20060197557 - Self dc-bias high frequency logic gate, high frequency nand gate and high frequency nor gate: A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupled to an impedance matching network. The impedance...