Electronic digital logic circuitry inventions 08/06

20060192586 - Reconfigurable sequencer structure: A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory...

20060192587 - Self-bypassing voltage level translator circuit: A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal...

20060192588 - Differential output circuit and semiconductor device having the same: A differential output circuit first and second transistors forming a differential pair and having control electrodes input with binary signals, a constant current circuit supplying a constant current to the first and second transistors, and a protection circuit protecting the first and second transistors from external noise. The protection circuit...

20060192589 - Inverter apparatus with improved gate drive for power mosfet: An inverter apparatus is composed of a power MOSFET having a source/drain connected to an output terminal, and a gate drive circuit driving a gate of the power MOSFET. The gate drive circuit includes a discharging path connected with the gate of the power MOSFET. The discharging path includes a...

20060192590 - Differential switching circuit and digital-to-analog converter: A differential switching circuit has a first transistor connected between a first output node and a common node and a second transistor connected between a second output node and the common node. A switching driver generates first and second driving signals in response to an input data signal so as...

20060192591 - Logic circuits utilizing gated diode sensing: A family of logic circuits, called gated diode logic circuits, is disclosed wherein small amplitude signals, typically a fraction of the supply voltage, can be sensed and amplified by applying a small amplitude signal to a gate of a gated diode in a sampling mode and changing a voltage of...

20060186915 - Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied...

20060186916 - Digital audio system on a chip: A GPIO cell of a SOC functions, in a first state, to pass an output signal from one of plurality of modules of the SOC to a pin when an output enable signal is activated. The GPIO cell further functions, in a second state, to pass an alternate output signal...

20060186917 - I/o circuitry shared between processor and programmable logic portions of an integrated circuit: The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins....

20060186919 - Dedicated logic cells employing configurable logic and dedicated logic functions: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two...

20060186918 - Dedicated logic cells employing sequential logic and control logic functions: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two...

20060186920 - Inter-tile buffer system for a field programmable gate array: An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to...

20060186921 - Dual-voltage three-state buffer circuit with simplified tri-state level shifter: A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control...

20060186922 - Translator circuit and method therefor: In one embodiment, a voltage translator is configured to sense a change in a value of a supply voltage to the translator and responsively inhibit the translator from changing a state of the output of the translator....

20060186923 - Interface circuit: An interface circuit includes a first and a second input terminal, a first output transistor, a second output transistor, a first output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of...

20060186924 - Voltage-level converter: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up...

20060186925 - Tie-high and tie-low circuit: A tie-high, tie-low circuit having a tie-high output and a tie-low output comprises a regenerative device to be coupled with both the tie-high and the tie-low outputs, and at least a PMOS device and a NMOS device to be coupled respectively with a high voltage and a low voltage. A...

20060181302 - Slew rate control for driver circuit: The slew rate of signals output from an integrated circuit is selectively controlled to optimize the quality of the output data signal depending upon whether the communication channels require a faster or slower slew rate. Faster slew rates may be utilized when the communication channels are prone to attenuation, while...

20060181303 - Data receiver with a programmable reference voltage to optimize timing jitter: Pseudo-differential drivers and receivers are used to communicate data signals between two or more IC chips. The data paths are aligned using programmable delay circuitry to de-skew each data path. A programmable reference generator is used to generate a reference voltage used by one or a group of receivers to...

20060181304 - Logic line driver system for providing an optimal driver characteristic: A line driver for off-chip communication comprises multiple parallel stages each with separate inputs. The parallel stages each have a controlled impedance when driving the line driver output node to a logic zero or a logic one. A line driver controller is used to select what combination of driver stages...

20060181305 - Integrated circuit including programmable logic and external-device chip-enable override control: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a...

20060181306 - Multi-threshold cmos system and methods for controlling respective blocks: A multi-threshold CMOS system and method controls a state of respective blocks individually. Each block includes a logic circuit having a logic transistor and a control transistor connected between the logic circuit and a power line connected to one of a ground and a power source. The control transistor has...

20060181308 - Programmable structured arrays: A programmable semiconductor device, wherein: a user programmable switch comprising a configurable element is positioned above a transistor gate material layer deposited on a silicon substrate layer....

20060181307 - Semiconductor integrated circuit and method for laying-out and wiring the semiconductor integrated circuit: A semiconductor integrated circuit includes a plurality of rows of wired standard cells formed on a semiconductor substrate. The wires standard cells are wired to provide a desired function. Spare standard cells are also formed in each of the plurality of rows in an area in which the wired standard...

20060181309 - Semiconductor device and layout design method for the same: A rectangular opening is formed in a power supply line which is shared between cell rows. A connection to a substrate potential supply line is ensured in the rectangular opening....

20060181310 - Exclusive-or and/or exclusive-nor circuits including output switches and related methods: An exclusive-OR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-OR circuit may also include a switch configured to couple an output signal of the NAND gate to an output node...

20060181311 - Circuit for generating an internal enabling signal for an output buffer of a memory: A circuit is for generating an internal enabling signal for the output buffer of a memory as a function of external commands for enabling the memory and for outputting data. The circuit may be input with the external command for enabling the memory and with internally generated flags signaling when...

20060181312 - Semiconductor device with adjustable signal drive power: A semiconductor device includes a terminal configured to receive a first signal that is set from an exterior at a time of operation, a memory unit configured to retain a state of a setting fixedly regardless of whether at the time of operation or at a time of no operation...

20060181313 - Transistor logic circuit: An input inverter section inverts a plurality of input signals to generate complementary signals and supplies signals complementary to these input signals to a logic circuit network. The logic circuit network comprises a plurality of pairs of depletion type NMOSs (NDMOSs) whose conducting states are respectively controlled on a complementary...

20060176073 - Clocked preconditioning of intermediate nodes: A clocked bleeder device is used to precondition an intermediate node of an integrated circuit. The clocked bleeder device is activated by a clock signal. The clock signal activates the bleeder device at a time in which the integrated circuit is inactive. The clock signal controls the period of time...

20060176074 - Differential termination and attenuator network for a measurement probe having an automated common mode termination voltage generator: A differential termination and attenuator network having an automated common mode termination voltage generator includes first and second termination resistors coupled in parallel with corresponding resistive attenuator circuits. A monitoring circuit coupled to input nodes of the network generates an output signal representative of the combination of a DC common...

20060176076 - Communication device for a logic circuit: A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse...

20060176075 - Customizable and programmable cell array: A semiconductor device may include a logic array having a multiplicity of inputs and a multiplicity of outputs and customized interconnections providing permanent direct interconnections among at least some of the multiplicity of inputs and at least some of the multiplicity of outputs....

20060176077 - Programmable application specific integrated circuit for communication and other applications: A programmable application specific integrated circuit (ASIC) for implementing operations that involve a plurality of computational functions. The programmable ASIC comprises a plurality of fixed functions and programmable switch logic. Each of the plurality of fixed functions is parameterized such that its operational characteristics are programmable using different operating parameters....

20060176078 - Voltage level shifting circuit and method: A voltage level shifting circuit and method that can be used for shifting the voltage level of an input signal to provide an output signal having a higher output voltage level. The voltage level shifting circuit includes pull-up transistors that are switched OFF by the voltage of a pair of...

20060176079 - Input/output circuit of semiconductor memory device and input/output method thereof: An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data...

20060176080 - Power supply noise insensitive multiplexer: CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of two multiplexing methods. The first method places switches on the data inputs...

20060176081 - Fast pulse powered nor decode apparatus for semiconductor devices: A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage...

20060170449 - Differential amplifiers using asymmetric transfer characteristics to suppress input noise in output logic signals: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission...

20060170450 - Integrated circuit with programmable-impedance output buffer and method therefor: An impedance matching between two integrated circuits is achieved using an impedance measuring circuit in the integrated circuit that contains an impedance-programmable output buffer (IPOB) that is to have its output impedance changed. The impedance measuring device is directly connected to the output of the IPOB so that it is...

20060170451 - Systems and methods for reducing electromagnetic emissions from a controller area network transceiver: Systems are provided for reducing electromagnetic emissions from a controller area network transceiver. A driver circuit is operative to transmit communications across an associated bus. A static driver replica circuit approximates a common-mode voltage associated with a dominant state associated with the bus. A receiver attenuator bias circuit forces a...

20060170453 - Low latency multi-level communication interface: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two...

20060170452 - System and method for generating a trigger signal: One disclosed embodiment may comprise an application specific integrated circuit (ASIC). The ASIC includes memory that stores condition data defining conditions for enabling transitions among a plurality of states and next state data defining a next state associated with each of the respective conditions. A state machine circuit employs the...

20060170454 - Level shifter having extended input level: A level shifter for level shifting an input signal from a first level to an output signal having a second level includes an operation range extension portion configured to extend an input range of the level shifter and to generate a first extension control signal in response to the input...

20060170456 - Driver circuit for binary signals: The invention relates to a driver circuit for binary signals, said circuit having two branch circuits which are connected in parallel with one another between an input node and an output node, the first of which branch circuits contains an output stage which, in response to the first binary value...

20060170455 - Method and circuit for maintaininig i/o pad characteristics across different i/o supply voltages: A circuit implements a method to adjust input/output (I/O) characteristics of an I/O pad circuit (10) depending upon which value of an I/O supply voltage is used within a range of supply voltages. An I/O supply voltage being supplied to the pad circuit is detected by detecting (18, 20) its...

20060170457 - Configurable high / low side driver using a low-side fet pre-driver: A high-side driver circuit for driving a load, including a low-side driver IC having a drive output and a feedback input, a first transistor coupled to the drive output, and a second transistor coupled between a power source and the load. The second transistor is configured to enter an “OFF”...

20060170458 - Output buffer with improved slew rate and method thereof: An output buffer with an improved slew rate and method thereof. The output buffer may include a differential amplifier, a controller and an output unit. The output buffer may generate a pull signal and a control signal based on received input and output signals. The controller may transition an output...

20060170459 - Multiplexer and methods thereof: A multiplexer and methods thereof. In an example, the multiplexer may receive a first periodic signal with a first active duration and a second periodic signal with a second active duration, the first and second active durations not overlapping. The multiplexer may transition statuses of first and second transmission gates...