Electronic digital logic circuitry inventions 07/06

20060164119 - Electronic circuit with array of programmable logic cells: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The...

20060164120 - Programmable logic cells with local connections: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers...

20060164121 - Structured integrated circuit device: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with...

20060164122 - Level shifter: The level shifter comprises a coupling block, a PMOS switch, a first PMOS transistor and a second PMOS transistor. The coupling block receives a first signal and a second signal to generate a first control signal and a first reference voltage. The first signal and the second signal are of...

20060164123 - Self-programmable bidirectional buffer circuit and method: The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes. The method includes applying a configuration signal on one of...

20060164124 - Magnetic logic device: A method for operating a magnetic logic device (10) is described wherein at least one output variable O=F (IA, IB) is formed from input variables (IA, IB) by at least one logic operation with an operator function F of the magnetic logic device (10), whereby the logic device (10) is...

20060158214 - Apparatus and method for independent control of on-die termination for ouput buffers of a memory device: An apparatus and method providing independent control of on-die termination (ODT) of output buffers. The ODTs for the buffer circuits of an input/output (I/O) buffer can be enabled and disabled in response to an ODT control signal. Additionally, the ODTs for a first set of the buffer circuits can be...

20060158213 - Apparatus and method of tuning a digitally controlled input/output driver: Apparatus and method of tuning a digitally controlled input/output (I/O) driver of an integrated circuit for parameter variation compensation, a bus impedance of the I/O driver being controlled by a first digital code comprises in one embodiment: controlling a bus impedance of a reference I/O driver network by a second...

20060158216 - Semiconductor integrated circuit device: A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance...

20060158215 - Technology for supressing noise of data bus circuit: A data bus circuit connects a south bridge driven by a first voltage and a bay driven by a second voltage. The first voltage and the second voltage are different. The data bus circuit includes a data bus that electrically connects the south bridge and the bay, and a Thevenin...

20060158217 - Timing exact design conversions from fpga to asic: Timing exact design conversions from an original field programmable device to an application specific device is disclosed. In a first aspect, a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC) comprises a user configurable element in the FPGA replaced by a mask...

20060158218 - Electronic circuit with array of programmable logic cells: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. In a...

20060158220 - Methods of reducing power in programmable logic devices using low voltage swing for routing signals: Reduced voltage swing signal path circuitry is provided that lowers the internal signaling power consumption of the interconnection resources of a programmable logic device. The reduced voltage swing signal path circuitry includes a reversed routing driver circuitry to limit the voltage range of the output signal of the driver circuitry....

20060158219 - Programmable logic and routing blocks with dedicated lines: A programmable logic structure is disclosed that has a set of dedicated lines which extends internally throughout different dedicated logic cells within a logic and routing block (LRB), extends from a previous logic routing block to the present logic and routing block, or extends from the present logic and routing...

20060158221 - Logic circuit combining exclusive or gate and exclusive nor gate: A logic circuit combining an exclusive OR gate and an exclusive NOR gate is provided. The logic circuit includes an NMOS transistor, a PMOS transistor, and first and second inverters. The NMOS transistor has a source connected to a first input signal, a drain connected to a first output signal,...

20060158222 - Testing using independently controllable voltage islands: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to...

20060158223 - Method and apparatus for multi-mode driver: Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according...

20060158225 - High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation: A signaling system having an equalizing transmitter and equalizing receiver. The equalizing transmitter transmits a signal to a receive circuit. A first sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a first threshold, and a second sampling circuit within the equalizing receiver samples...

20060158224 - Output driver with feedback slew rate control: An output driver circuit comprises a primary output driver and a secondary output driver, where the primary and secondary output drivers have outputs at an output terminal and inputs at an input terminal. A slew rate control circuit is provided for disabling the secondary output driver in response to a...

20060158226 - Inverting dynamic register with data-dependent hold time reduction mechanism: A dynamic logic register including evaluation logic, delay logic, and latching logic. The evaluation logic evaluates a logic function based on data input. The logic function evaluates to either a first state or a second state. The delay logic generates a kill signal, where the kill signal is a delayed...

20060158227 - Complimentary metal oxide silicon low voltage positive emitter coupled logic buffer: A low voltage positive emitter coupled logic (LV-PECL) buffer fabricated in the complimentary oxide metal silicon (CMOS) process. The LV-PECL buffer in CMOS is operable for a wide frequency range from DC to frequencies as high as 800 MHZ in 0.5 um process. Synchronized feedforward logic is utilized without the...

20060152246 - Method and apparatus for configuring the operation of an integrated circuit: Method and apparatus for configuring the operation of an integrated circuit. An integrated circuit with external programming capabilities is disclosed. A pin current source is provided for interfacing with at least one pin on the integrated circuit to control current flow there through to an external load interfaced to the...

20060152247 - System and method for reducing power consumption associated with the capacitance of inactive portions of a multiplexer: Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding...

20060152248 - Configuration circuits for programmable logic devices: Configuration circuits wherein configurable elements comprise low conducting on currents and/or low on to off current ratios for programmable logic devices are disclosed. A semiconductor device, wherein: a programmable logic circuit is configured by a control signal received at a capacitive node in the circuit, wherein the control signal is...

20060152249 - Configuration circuit for programmable logic devices: A configuration circuit, comprising: a configurable storage element coupled between a ground voltage and a first voltage, said storage element generating an output; and a voltage conversion circuit coupled between the ground voltage and a second voltage at a lower level than said first voltage, said circuit further coupled to...

20060145722 - Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects...

20060145723 - Voltage level conversion circuit: A voltage level conversion circuit for converting a voltage level of a low voltage system input signal into a voltage level of a high voltage system signal comprises a latch circuit comprising plural high-breakdown-voltage MOS transistors having a high power supply voltage as a breakdown voltage, a first high-breakdown-voltage N...

20060145724 - Relatively low standby power: Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the combinational logic gates, leakage current may be reduced and state, or other, values to be used for subsequent operations may be...

20060145725 - Relatively low standby power: Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the combinational logic gates, leakage current may be reduced and state, or other, values to be used for subsequent operations may be...

20060145726 - Low power consumption mis semiconductor device: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation...