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Electronic digital logic circuitry June invention type 06/06

20060139050 - Circuit for transmitting high frequency signals: A transmission circuit for transmitting an IEEE 1394b signal includes a driving circuit, a load circuit connected to the driving circuit, a first signal line and a second signal line connected to the load circuit, an IEEE 1394b interface, a first resistor, a second resistor, and a third resistor. Two...

20060139051 - Variable impedence output buffer: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the...

20060139052 - Semiconductor integrated circuits with power reduction mechanism: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element...

20060139053 - Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an fpga: A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed...

20060139054 - Look-up table structure with embedded carry logic: A multiple input look up table (LUT) structure adapted for carry-logic implementation, wherein each input is received in true and compliment levels, comprising: an output of an intermediate stage within the LUT structure; and a LUT value input of a stage next to said intermediate stage; and a multiplexer (MUX)...

20060139056 - Field programmable structured arrays: A programmable semiconductor device wherein a programmable switch and a configuration element to program the switch are both positioned above a first metal layer....

20060139055 - Interconnect structure enabling indirect routing in programmable logic: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in...

20060139057 - Structured integrated circuit device: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with...

20060139058 - Supply enabled optimization output buffer: An output buffer having a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level and controls the voltage at the...

20060139059 - Level shift circuit and method: We describe various embodiments of a level shift circuit and an associated method that achieve increased responsiveness by simultaneously adjusting the input signal width and shifting the voltage thereby reducing the number of logic gate stages needed for the two operations. A level shift circuit includes a delay unit for...

20060139060 - Semiconductor memory device: A semiconductor memory device is capable of adjusting effective data period of data. The semiconductor memory device includes a buffering unit for buffering input data, a window adjusting unit, and a transmitting unit. The window adjusting unit is for adjusting a window of the buffered data outputted from the buffering...

20060139061 - Protected set dominant latch: In some embodiments, a set dominant latch with an input node and a state node is provided the circuit includes at least one driver gate coupled to the state node and to the input node to provide a driven output of the state node. Other embodiments are disclosed and/or otherwise...

20060132168 - Tunneling diode logic ic using cml-type input driving circuit configuration and monostable bistable transition logic element (mobile): The present invention relates to CML(Current Mode Logic)-type input driving method and tunneling diode logic using MOBILE(Monostable Nistable transition Logic Element) configuration, as kinds of very high-speed digital logic circuits. The objectives of the present invention are to improve the disadvantage of MOBILE circuit configuration that is an existing tunneling...

20060132169 - Circuit re-synthesis and method for delay variation tolerance: By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in the IC industries to improve the yield in semiconductor manufacturing....

20060132170 - Device for a two-wire line terminal: A device for a line termination of two-wire lines having at least one first and second terminating resistant between the two wires is provided, the first and the second terminating resistors being connected in series, and at least one switching arrangement being provided between the two terminating resistors....

20060132171 - Integrated circuit device with controllable on-die impedance: Described are controllable impedances that may be adjusted by a combination of digital and analog signals. An adjustable impedance responsive to the digital signals establishes a gross resistance between two nodes by enabling one or more of a plurality of parallel-coupled impedance legs. Each leg includes at least one transistor...

20060132172 - Digital sampling frequency converter: The present invention relates to a converter converting an input digital signal into an output digital signal. Said converter comprises in particular a set of shift registers able to contain samples of the input or output digital signal. It also comprises a calculation unit able to supply a shift signal...

20060132173 - Over-voltage tolerant bus hold circuit and method therefor: In one embodiment a bus hold circuit decouples an inverter of the bus hold circuit from an operating voltage responsively to an input receiving a signal having a voltage that is approximately equal to or greater than the value of the operating voltage....

20060132175 - Look-up table based logic macro-cells: A programmable look up table (LUT) structure that offers higher logic packing capacity over conventional LUT structures for programmable logic devices is disclosed. A programmable LUT structure comprising a first stage and one or more intermediate stages and a last stage, wherein at least one of said intermediate stages or...

20060132174 - Reconfigurable semitransparent optical switching device: Each broadcast module includes a programmable demultiplexer module (IWS1-IWS3) having a transit output (B1) and a selection output (B2) and a star coupler (SC1-SC3). The transit output (B1) is connected to a first input (C1) of the coupler and an input and an output of a processing device (RG, RG′)...

20060132176 - Merged logic element routing multiplexer: A merged logic element routing multiplexer circuit includes one or more inputs coupled to the logic element (LE) output, one or more tri-stated circuits coupled to the corresponding one or more inputs, wherein the tri-stated circuits are controlled by a set of programmable select signals, and an output port coupled...

20060132177 - Linear buffer: A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the...

20060132178 - Pin multiplexing: There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core for operation of a first function, a second core for operation of a second function, a multiplexer and an additional hardware module. The multiplexer is arranged to...

20060132180 - Current driver, data driver, and display device: In a current driver, a gate of a first generating transistor, gates of K driving transistors, and a gate of a second generating transistor are connected to a gate line in this order. A first differential amplifier outputs a voltage determined according to the difference between a voltage from a...

20060132179 - Low voltage differential signaling drivers including branches with series resistors: A low voltage differential signal driver includes first and second current sources, a first branch and a second branch. The first branch includes at least two transistors and at least two resistors between them that are all connected in series between the first and second current sources, to define a...

20060132182 - Driver circuit, shift register, and liquid crystal driver circuit: A driver circuit according to the present invention includes a transistor for outputting a voltage input from a drain as an output signal from a source, a first capacitor disposed between a gate and the source of the output transistor to increase an application voltage applied to the gate, and...

20060132181 - Multipath input buffer circuits: Provided is a multi-path input buffer circuit, which passes a signal input to a semiconductor device through different paths in consideration of the voltage level of the input signal. The multi-path input buffer circuit includes an input buffer stage, which can be driven using one of at least two power...

20060132183 - Semiconductor device: A semiconductor device that performs stable circuit operations is provided. The device includes: a pull-up driver for pulling up a first node in response to first states of input and control signals; a pull-down driver for pulling down a second node in response to a second state of the input...

20060132184 - Systems and methods for reducing timing variations by adjusting buffer drivability: Systems and methods for reducing variations in the timing of signal transitions which may result from interference with neighboring signal lines by adjusting the drivability of in-line buffers based upon the hostile/friendly condition of the neighboring lines. In one embodiment, a first inverter includes selectable current paths between the buffer...

20060132185 - Clock gating circuit: Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the...

20060132187 - Body biasing for dynamic circuit: In some embodiments, a circuit is provided that comprises a dynamic circuit and a body bias circuit. The dynamic circuit has a keeper transistor. The body bias circuit is coupled to the keeper transistor and is configured to body bias the keeper transistor in accordance with a leakage associated with...

20060132186 - Dynamic phase assignment optimization using skewed static buffers in place of dynamic buffers: A primarily domino logic block uses static buffers instead of clocked domino buffers to correct a phase skipping problem, while realizing the same logic function with less integrated circuit area, power consumption, and cost. The use of static buffers simplifies the clock network and clock tree synthesis. A domino logic...

20060132188 - Unfooted domino logic circuit and method: A domino clocking method includes providing a domino logic circuit including first and second coupled domino gates, providing a first clock signal for clocking the first domino gate, and providing a second clock signal for clocking the second domino gate, wherein the first clock signal has a shortened positive phase...

20060125514 - Semiconductor integrated circuit having interface circuit containing pull-up resistor and blocking diode, circuit module including such integrated circuit, and electronic apparatus including such circuit modules: In a semiconductor integrated circuit having an interface circuit adapted to be connected to a power supply line connected to the interface circuit, and a signal line connected to the interface circuit. A pull-up resistor is connected to the power supply line at one terminal thereof. A blocking diode has...

20060125516 - Method and circuit for off chip driver control, and memory device using same: An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word....

20060125515 - System for transmission line termination by signal cancellation: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single...

20060125518 - Shift register and display driving device comprising the same: A shift circuit of a shift register includes an output terminal, an input terminal, a reset terminal. A voltage is applied to a first wiring in response to the output signal from the preceding stage shift circuit to the input terminal and in accordance with the predetermined voltage to the...

20060125517 - Techniques for optimizing design of a hard intellectual property block for data transmission: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel...

20060125519 - Programmable logic array: A programmable logic array (PLA) which may include an AND-plane receiving first input signals and generating logic product signals based on the first input signals, and an OR-plane receiving the logic product signals and a second input signal and generating a logic sum signal based on the logic product signals....

20060125520 - Method to improve current and slew rate ratio of off-chip drivers: An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided. Variations in process conditions may result in stronger or weaker relative current drive between NMOS and PMOS transistors. One or more process-dependent compensating current paths may...

20060125521 - Level shifter and level shifting method: A level shifter and method of level shifting between an input signal and an output signal which may realize improvement s in operating speed and reductions in power consumption. An example level shifter may include a pull-up signal generation unit outputting a pull-up signal at a voltage level that is...

20060125523 - Input circuit and method: We describe an input circuit and method. The input circuit includes a variable reference level generator that increases a level of a reference signal in proportion to a time when an input signal transits from a low level to a high level and decreases the level of the reference signal...

20060125522 - Output stage, amplifier control loop and use of the output stage: An output stage includes a first transistor pair with a first conductivity type and a second transistor pair with a second conductivity type. The source connections of the first and second transistors in the first transistor pair and of the first and second transistors in the second transistor pair are...

20060125524 - Output circuit: An output circuit for a circuit includes an input node coupled to the circuit, an output node, a reference potential terminal, a supply potential terminal, a semiconductor switch connected between the input node and the output node, and a control circuit. The control circuit is designed to open the semiconductor...

20060125525 - Driving method of an electric circuit: A variation in threshold may be suppressed by structuring an analog switch by a MOS transistor and forming a signal synchronized to a clock by making the clock which is a common signal in continuity or discontinuity. An object of the present invention is to reduce the variation in the...

20060125526 - Differential analog logic circuit with symmetric inputs and output: A logic circuit incorporates symmetric inputs and/or a symmetric output. The logic circuit may include symmetric input circuits such that each input signal may be processed by a circuit that provides substantially identical rise times and fall times. The input circuits may provide symmetric loading of the input signals by...

20060125527 - Interface system and method therefor: In one embodiment, a differential transistor pair of an ECL differential amplifier is formed on two different semiconductor die....

20060114016 - Semiconductor device: A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set at 50 ohms which is equal to the characteristics impedance of...

20060114017 - Adjusting settings of an i/o circuit for process, voltage, and/or temperature variations: A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and...

20060114018 - Reconfigurable logical circuit using transistor having spi-dependent transmission characteristics: A nonvolatilely reconfigurable logical circuit is built It is a reconfigurable logical circuit based on the CMOS configuration using the spin MOSFET. By changing the transmission characteristic of each transistor in accordance with the magnetization states of Tr1, Tr2, Tr5, and Tr8 which are spin MOSFETs, it is possible to...

20060114019 - Low voltage logic operation using higher voltage supply levels: A circuit comprises 2n modules that are connected in series between first and second reference potentials. 2n−1 nodes that are arranged between adjacent ones of said 2n modules. 2n−1 2:1 DC/DC converters, wherein each of said 2n−1 2:1 DC/DC converters communicates with a respective one of said 2n−1 nodes....

20060114020 - One time programmable latch and method: A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according...

20060114021 - Selector circuit: A plurality of conduction control circuits controls conduction of input signals. A logical operation circuit receives output signals from each of the conduction control circuits via a plurality of signal paths, and performs a logical operation on each of the output signals to output a single signal. A signal-level setting...

20060114022 - Output reporting techniques for hard intellectual property blocks: Techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block on an integrated circuit are provided. By reducing the frequency of the output signal, circuit blocks in the integrated circuit that operate at a lower frequency than the HIP block are able to capture...

20060114023 - Floor plan for scalable multiple level tab oriented interconnect architecture: A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the first level routing resources through tab networks; each tab network...

20060114024 - Tileable field-programmable gate array architecture: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals,...

20060114025 - Design method and architecture for power gate switch placement: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated...

20060114027 - Low voltage logic operation using higher voltage supply levels: A network device comprises a first channel module, a second channel module in series with the first channel module, a third channel module in series with the second channel module, and a fourth channel module in series with the third channel module. The first and fourth modules are connected in...

20060114026 - Tracking unity gain for edge rate and timing control: In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a unity gain detector to traverse a gain curve of an output buffer circuit to determine unity gain voltages associated with unity gain crossover points on an input voltage ramp. The apparatus further includes...

20060114028 - Method and apparatus to generate break before make signals for high speed ttl driver: A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes...

20060114029 - Domino logic compatible scannable flip-flop: A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The...

20060114030 - Circuit wiring layout in semiconductor memory device: A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS...