Electronic digital logic circuitry inventions 05/06

20060109026 - Line reflection reduction with energy-recovery driver: A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from...

20060109027 - Programmable logic cell: For a programmable logic cell, an output assumes a value, which is dependent on values of inputs and on a Boolean function, which determines a value for the output for each setting of the inputs. The logic cell includes at least one ALU and additional logic via which the Boolean...

20060109028 - Single-stage and multi-stage low power interconnect architectures: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second...

20060109029 - Logic circuit: Disclosed is a logic circuit including first and second input terminals, supplied with respective logic signals, and first and second MOS transistors, having sources respectively connected to associated ones of the first and second input terminals and gates cross-connected to the second and first input terminals. The drains of the...

20060109030 - Single-supply voltage translator input having low supply current: A voltage translator circuit is disclosed herein that eliminates the need for two supply voltages to achieve voltage translation through the use of supplying a shifted voltage threshold. Effectively, this voltage translator circuit has very little supply current (Icc) after the device switches. Specifically, the voltage translator in accordance with...

20060109031 - Complementary pass-transistor logic circuit and semiconductor device: A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input nodes and the intermediate nodes, and the conduction states of the transistors being controlled by second complementary...

20060103418 - Methods and systems for rise-time improvements in differential signal outputs: A method for maintaining signal integrity of a differential output signal generated from a differential driver is disclosed. The method includes receiving the differential output signal from the differential driver. Once received, the method includes tuning the differential output signal by exposing the differential output signal to an inductance. The...

20060103419 - Programmable logic device including multipliers and configurations thereof to reduce resource utilization: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This...

20060103420 - Switch block and corresponding switch matrix, in particular for fpga architectures: A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted...

20060103421 - System-in-package type semiconductor device: A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111, and first ground wiring 1112 to which the first circuit unit is coupled. Moreover, the system-in-package type semiconductor device includes a second...

20060103422 - Low leakage, source modulated, differential output level shifter: Disclosed is a low leakage, source modulated, differential output level shifter that has reduced duty-cycle distortion and better crossover symmetry. The system utilizes P-type assisting transistors that drive the sources of the P-type cross-connected transistors in the level shifter. In this fashion, the width to length ratio of the N-type...

20060103423 - Buffer circuit: A buffer circuit for reducing leakage current and for protecting circuits from electrostatic discharge (“ESD”). A power supply circuit of an input/output buffer includes a transistor circuit connected to a high-potential power supply, a transistor circuit connected to a low-potential power supply, and a protection circuit connected between the two...

20060103426 - Compensation circuits for unequal input/output common mode voltages: A circuit apparatus having compensation circuits for unequal input/output common mode voltages is presented. The apparatus includes a circuit unit, a feedback path and a current source. The circuit unit has at least an input terminal for receiving an input signal and at least an output terminal for generating an...

20060103424 - Low-power low-voltage multi-level variable-resistor line driver: A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors is disclosed for transmitting digital data over controlled-impedance transmission lines. The driver comprises two push-pull variable resistor branches, and a middle variable resistor branch. The purpose of the two push-pull branches is to generate the target voltage level...

20060103425 - Output buffer stage: The output buffer stage includes a half-bridge output stage having a first pair of complementary drivers connected in series between a supply line and a ground node, the high impedance state or conduction state of which is determined through a pair of control phases. The buffer stage includes a pair...

20060103427 - Overvoltage tolerant input buffer: When a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transistor in such a way that it is turned...

20060103428 - Semiconductor integrated circuit: To provide an output MOS transistor from breaking due to dump surge and counter electromotive, a semiconductor integrated circuit according to an embodiment of the invention includes an output MOS transistor controlling current flowing through a load, a dynamic clamp circuit clamping an overvoltage applied to the output MOS transistor,...

20060103429 - Bootstrap circuit and driving method thereof: A bootstrap circuit includes an output transistor, a bootstrap capacitor provided between the gate and source of the output transistor, a power source, and a circuit that performs ON/OFF control of a supply from the power source to the gate electrode of the transistor. An initial voltage before a bootstrap...

20060103430 - Leakage-tolerant dynamic wide-nor circuit structure: One embodiment of the present invention provides a circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure. The circuit contains a precharge device which is coupled to the dynamic node. The precharge device precharges the dynamic node during a...

20060103431 - Dynamic logic circuit incorporating reduced leakage state-retaining devices: A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except...

20060097747 - Superconducting qubit with a plurality of capacitive couplings: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the...

20060097746 - Superconducting qubits having a plurality of capacitive couplings: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the...

20060097748 - Semiconductor device and communications terminal and automobile having the same: A semiconductor device is disclosed in which resistance to the influence of external noise on internal power source network is improved. A semiconductor device operating at any predetermined frequency among a plurality thereof, and having power source networks for supplying power from a power source to internal functional units in...

20060097749 - Dynamic impedance compensation circuit and method: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel...

20060097750 - Electronic circuit with array of programmable logic cells: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The...

20060097752 - Lut based multiplexers: An improved LUT based multiplexer, including a first set of muxlets, each receiving a subset of input data lines at its inputs and one or more muxlet stages cascaded together to form a tree structure in which the roots are the first set of muxlets and the last stage of...

20060097751 - Programmable logic array latch: A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array....

20060097753 - Transmitter circuit, receiver circuit, interface circuit, and electronic instrument: A transmitter circuit including: a current driver which current-drives differential signal lines; and a voltage driver which is electrically disconnected from at least one of the differential signal lines in a normal transfer mode, and is electrically connected to the at least one of the differential signal lines and voltage-drives...

20060097754 - Gated clock logic circuit: A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and a control signal....

20060091899 - Programmable logic device: The present invention aims to provide a programmable logic device (PLD), and a related control program, capable of improving a product yield by avoiding a defect point according to defect point detected after PLD fabrication. The PLD includes a plurality of logical blocks including programmable logic circuits; storage in which...

20060091900 - Semiconductor memory device with on die termination circuit: A semiconductor memory device having a data input/output pad connected to a data input node includes: an on die termination resistor one end of which is connected to the data input node; and a switch one end of which is connected to the other end of the on die termination...

20060091901 - Semiconductor memory device with on-die termination circuit: An on-die termination circuit with a stable effective termination resistance value and stabilized impedance mismatching. The on-die termination circuit includes: a decoding unit for decoding set values of an extended mode register set; an ODT output driver block including a plurality of output driver units connected in parallel with an...

20060091902 - Data input buffer in semiconductor device: A data input buffer for use in a semiconductor device, including: a detection unit for receiving a reference voltage signal and an input data signal through a first input terminal and a second input terminal respectively in order to detect a voltage level of the input data signal based on...

20060091903 - Configurable logic device providing enhanced flexibility, scalability and providing area efficient implementation of arithmetic operation on n-bit variables: The configurable logic device provides enhanced flexibility, scalability and area efficient implementation of arithmetic operation on (N−1) bit variables. The device includes a first configurable logic subsystem capable of generating logic OR output in response to functions of N−1 input variables in arithmetic mode, a second configurable logic subsystem capable...

20060091905 - Method and apparatus for a chaotic computing module: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic...

20060091904 - Method and apparatus for efficient utilization of electronic fuse source connections: A method for and an apparatus in which the FSOURCE connection in a fuse domain is split into multiple nets, allowing flexible placement of primary fuses in the floorplan, is provided. In particular, multiple FSOURCE connections (e.g. C4 pads or wire pads) are provided in the floorplan, allowing flexible placement...

20060091906 - Integrated circuit provided with core unit and input and output unit: A core unit implements a predetermined function. An I/O unit controls input from and output to the outside. The core unit and the I/O unit are subject-to independent control for supply of power. When power is turned off in the core unit, a signal output from the I/O unit to...

20060091907 - High speed buffered level-up shifters: Embodiments of the invention include apparatus with a level-up shifter including a comparator having a pair of cross coupled PFETs with sources coupled to an I/O power supply and gates coupled to each other's drain, and a differential pair of NFETs with sources coupled to ground and gates respectively coupled...

20060091908 - Level shift circuit for use in semiconductor device: A level shifter for use in a semiconductor device, includes: a first transferring unit for transferring an input signal to an inverted output node in response to a negative voltage; a second transferring unit for supplying a power supply voltage to an output node in response to the input signal;...

20060091910 - Driving circuit of an output buffer stage having a high speed and a reduced noise induced on power supply: A driving circuit is for an output buffer stage, with high speed and reduced noise induced on the power supply. The driving circuit may include first and second circuit portions, each intended for the generation of a respective driving signal for a corresponding transistor of the buffer stage. Each portion...

20060091909 - Energy conserving, digital circuit driving a transmission line: In a digital system a circuit differentially drives a transmission line, which is open or lightly loaded at the receiving end. A change from a logical ‘1’ to a logical ‘0’ or vice versa is initiated by shorting the two conductors of the transmission line at the transmitting end. A...

20060091911 - Semiconductor memory device: An output driver for use in a semiconductor memory device includes a pull-up metal oxide semiconductor (MOS) transistor for pulling-up a voltage loaded on an output node in response to a pull-up control signal; a pull-up linear element connected between the pull-up MOS transistor and the output node for increasing...

20060091912 - Synchronization of clock signals in a multi-clock domain: A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge in an input clock signal after a logic low corresponding to a prior negative edge is propagated to as...

20060091913 - Power gating techniques able to have data retention and variability immunity properties: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed...

20060091914 - Spin-orbital quantum cellular automata logic devices and systems: Spin-orbital quantum cellular automata logic devices and integrated circuits in the form of a substrate having a thin film of material on the substrate having strongly coupled spin-orbital states, the thin film being patterned to define at least one input and at least one output, and to perform at least...