Electronic digital logic circuitry inventions 04/06

20060087338 - Power delivery noise cancellation mechanism: An integrated circuit is disclosed. The integrated circuit includes a power delivery network (PDN), a first voltage rail coupled to the PDN, an input/output (I/O) buffer coupled to the first voltage rail and a driver coupled to the I/O buffer. The driver transmits a current waveform to the I/O buffer...

20060087339 - Impedance adjustment circuits and methods using replicas of variable impedance circuits: An impedance adjustment circuit for controlling an impedance of a variable impedance circuit includes a calibration circuit including a replica of the variable impedance circuit and configured to generate an impedance control signal for the variable impedance circuit based on a voltage generated at the replica of the variable impedance...

20060087340 - Voltage tolerant protection circuit for input buffer: An improved voltage tolerant protection circuit for input buffer comprising a transmission gate circuit receiving input from the pad for passing the input signal to the input of the input buffer, a control signal generator electrically coupled between the transmission gate circuit and the pad to provide a control signal...

20060087341 - Dedicated input/output first in/first out module for a field programmable gate array: A field programmable gate array architecture having a plurality of input/output pads comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of...

20060087342 - Interconnect structure and method in programmable devices: An improved interconnect structure in programmable devices gives a new dimension to the routing architecture, where architecture is divided into various domains. It includes at least one set of input lines, each said set having predetermined number of input lines; an equal number of sets of routing lines, each said...

20060087343 - Semiconductor device: A semiconductor device includes insulated and separated transistor elements successively connected to one another between ground potential and a predetermined potential. A transistor element at the GND potential side is a first stage and a transistor element at the predetermined potential side is an n-th stage. Resistance elements or capacitance...

20060087344 - Nanoscale latches and impedance-encoded logic for use in nanoscale state machines, nanoscale pipelines, and in other nanoscale electronic circuits: Various embodiments of the present invention are directed to implementation and use of logic-state-storing, impedance-encoded nanoscale, impedance-encoded latches that store logic values as impedance states within nanoscale electronic circuits that employ impedance-driven logic. In certain of these embodiments, use of nanoscale, impedance-encoded latches together with nanoscale electronic circuits that employ...

20060087345 - Capacitance multiplier circuit exhibiting improved bandwidth: A monolithic capacitance multiplication circuit serves to reduce the required die area when larger capacitance values are needed such as in filter and loop frequency compensation circuits. A current mirror/cascoding device arrangement reduces the effective series resistance of the multiplier capacitor. As a result, the multiplier topology exhibits improved bandwidth...

20060082381 - Output circuit: Since voltages of two input terminals of an output unit having an online download function are decided by voltages which are not correlative to each other, a value of an incoming current on the start-up becomes large. The present invention solves the problem of turning-on of a parasitic transistor due...

20060082382 - Input circuit and an electronic control unit provided with such an input circuit: An input circuit commonly uses input ports of a microcomputer for a plurality of contact input terminals such as switches provided on the way to the ground. Transistors (Q1) to (Q8) whose bases are connected with contact input terminals (IN1) to (IN8) are provided. Groups of transistors, such as odd-numbered...

20060082383 - Pseudo differential output buffer, memory chip and memory system: An output buffer includes first and second input transistors, first and second output loads and a current source. The first and second input transistors have first current electrodes that are commonly coupled to each other and control electrodes that are respectively coupled to a first differential input signal and a...

20060082384 - Multi-threshold complementary metal-oxide semiconductor (mtcmos) bus circuit and method for reducing bus power consumption via pulsed standby switching: A multi-threshold complementary metal-oxide semiconductor (MTCMO) bus circuit reduces bus power consumption via a reduced circuit leakage standby and pulsed control of standby mode so that the advantages of MTCMOS repeater design are realized in dynamic operation. A pulse generator pulses the high-threshold voltage power supply rail standby switching devices...

20060082385 - Synchronous first-in/first-out block memory for a field programmable gate array: The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random...

20060082386 - Methods and systems for multi-state switching using multiple ternary switching inputs: Systems, methods and devices are described for placing a controlled device into a desired operating state in response to the position of a multi-position actuator. Two or more switch contacts provide input signals representative of the position of the actuator. Control logic then determines the desired state for -the controlled...

20060082387 - Energy recovery boost logic: A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage...

20060082389 - Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control: A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot...

20060082388 - Logic circuitry: A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit...

20060076974 - Architecture and interconnect scheme for programmable logic circuits: An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability between cells and accessibility to a hierarchical routing network. Uniformly distributed...

20060076975 - Reduced device count level shifter with power savings: A level shifting circuit includes an input node, an output node, a first power supply node, a second power supply node, a third power supply node, an inverter coupled to the first and second power supply nodes having an input coupled to the input node and an output, a transistor...

20060076976 - Data acceleration device and data transmission apparatus using the same: There is provided a data acceleration device comprising a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a...

20060076979 - Prestage for an off-chip driver (ocd): A prestage for generating a control signal for an output driver of an integrated circuit, wherein the integrated circuit can be provided with a reference potential and a supply potential fixed in relation to the reference potential, comprises an input for receiving an input signal from the integrated circuit, a...

20060076978 - Protection device for bus systems: An electrical protection device for bus systems, in particular having a two-wire design, including a bus-control unit and at least one device connected to a bus, the protection device being arranged in a central location on the bus and connected thereto....

20060076977 - Usb 1.1 for usb otg implementation: This invention enables a USB 1.1 device and a USB 1.1 host to communicate seamlessly with a USB OTG device. The invention complies with both USB 1.1 and OTG specifications. The invention includes the USB 1.1 host, USB 1.1 device and mixed signal circuits to implement USB OTG functions. The...

20060076980 - Output driver and method thereof: An output driver and method thereof. In the method, a current may be adjusted to adjust a power consumption in response to a change in a data rate. A first example output driver may include at least one transistor receiving at least one input signal, at least one resistor connected...

20060071683 - Calibration methods and circuits for optimized on-die termination: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a transmitter die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains the termination resistances for the signal transmission lines. The ODT...

20060071684 - Active storage area network discovery system and method: An active SAN discovery system and method responds to events occurring in SAN by automatically broadcasting for information related to the occurred events and updating the SAN topology according to the collected information....

20060071685 - Integrated circuit chip with high area utilization rate: An integrated circuit chip with a high area utilization rate includes: a plurality of logic circuits in a logic area; a first input and output circuit near a first side of the logic area for exchanging signals with the logic circuit; a second input and output circuit near a second...

20060071686 - Level shifter without dc current flow: A level shifter has a current mirror and a set of oppositely driven NMOS switch. A voltage holding module is added to help an output of the level shifter to work with a full-swing fashion. Additionally, a DC current switch is used to eliminate a DC current....

20060071688 - Output buffer circuit and semiconductor device: Disclosed is an output buffer circuit provided with a pre-emphasis function, including a first buffer circuit, receiving a first logic signal to drive a transmission line, and a second buffer circuit. The second buffer circuit includes an inverting buffer, receiving a second logic signal that is in a predetermined logical...

20060071687 - Output driver circuit with pre-emphasis function: In an output driver circuit and method, a control circuit generates a control signal in response to a current internal data signal. An output driver generates an output data signal in response to the control signal. A pre-emphasis circuit adjusts a current flowing through a node having the control signal...

20060071689 - Circuit and method for generating an output signal: A circuit comprises an output terminal, an output driver for providing an output signal at the output terminal, a switching device for producing one or more connections of the output terminal to a respective fixed or variable potential, and a control device for controlling the switching device, the control device...

20060071690 - Band gap reference voltage circuit: In a band gap reference voltage circuit, a band gap cell circuit composed of two transistors is driven with different current densities under a bias condition in which first and second reference voltages output in accordance with the operating states of the two transistors are equal to each other, thereby...

20060071691 - Input/output cells with localized clock routing: Described are approaches to routing buffered reference clock signals to a plurality of input/output (I/O) cell instances on an integrated circuit (IC) die. All or a subset of the I/O cell instances include clock routing resources optimized to deliver high-speed, low jitter clock signals within and through the particular instance....