Electronic digital logic circuitry inventions 12/05

20050285620 - Leakage testing for differential signal transceiver: A method includes providing a device under test (DUT) which has an input port and an output port. The DUT also has a squelch detector which is coupled to receive a signal from the input port. The DUT also has a receiver amplifier coupled to receive a signal from the...

20050285621 - Adaptive termination for optimum signal detection: An integrated circuit includes a number of terminals to transfer signals. Each of the terminals has an adjustable termination impedance. The integrated circuit also includes a control circuit coupled to the terminals to adjust the value of the termination impedance of each of the terminals to improve signal detection at...

20050285622 - Logic basic cell: A logic basic cell for processing a first and a second data signal, having a multiplex device for multiplexing the first and second data signals in a multiplex operating state, having a logic device for forming a logic combination of the first and second data signals in accordance with a...

20050285623 - Low-leakage level shifter with integrated firewall and method: A level shifter may reduce leakage current and provide firewall protection between circuits of different voltage domains when one voltage domain is in a standby mode. The level shifter may either couple or decouple input circuitry from a reference voltage in response to a firewall enable signal, may translate signals...

20050285624 - Hybrid pass gate level converting dual supply sequential circuit: A device comprising a receiving circuit to receive an input signal, a voltage level converting circuit and a biasing circuit. The receiving circuit including an output and a first latch circuit coupled to a first supply node. The voltage level converting circuit includes a second latch circuit coupled to a...

20050285625 - Semiconductor device, driving method thereof and electronic device: The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source drain voltage of one of two transistors connected in...

20050285626 - Circuits and methods of temperature compensation for refresh oscillator: A memory device has refresh cycles to refresh memory cells of the memory device. The time interval between one refresh cycle to the next refresh cycle is a refresh interval. The refresh interval depends on a frequency of an oscillating signal. A refresh timer adjusts the frequency of the oscillating...

20050285627 - Input enable/disable circuit: An integrated circuit control circuit disables the input circuit and the output circuit of the integrated circuit. On enabling the integrated circuit, the input circuit is enabled before the output circuit is enabled to prevent a race condition which generates a glitch in the output signal....

20050285628 - Charge recycling power gate: A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power...

20050285629 - Multiple signal format output buffer: An output buffer circuit drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety...

20050285630 - Multiple-output transistor logic circuit: A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate...

20050280436 - Nanotube-based logic driver circuits: Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output...

20050280435 - Output buffer with time varying source impedance for driving capacitively-terminated transmission lines: An output buffer for driving a capacitively-terminated transmission line produces a waveform which comprises a first portion during which the waveform transitions from a voltage V1 to a voltage V2; a second portion during which it remains fixed at V2; a third portion during which it transitions to a voltage...

20050280437 - Apparatus and methods for adjusting performance of integrated circuits: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias...

20050280438 - Switch methodology for mask-programmable logic devices: A mask-programmable logic device that implements a pre-existing circuit design and that includes programmable smart switches is provided. The smart switches are metal terminals that may be programmed to perform configuration-related logic functions of the pre-existing circuit design....

20050280441 - Integrated circuit: An integrated circuit includes a first and a second amplifier circuit (10, 20), which are in each case driven by an input signal (Vin) having a high and a low signal level and a reference signal (Vref) having a constant signal level and, on the output side (D11, D21) generate...

20050280440 - Predriver circuit: A predriver circuit that is capable of reducing the size of a drive transistor while preventing a drive transistor's gate from being destroyed, thereby reducing power consumption. The predriver circuit includes a current mirror circuit, which has a pair of transistors that are connected to a predriver power supply voltage;...

20050280443 - Power-aware configurable driver circuits for lines terminated by a load: The present invention provides a driver circuit for driving a line terminated by a load, wherein said driver circuit is configurable for design time selected energy/delay working points. The configuration capability is used, e.g. during run-time, for dynamically selecting a suitable energy/delay working point, given the circumstances wherein said driver...

20050280442 - Semiconductor integrated circuit: To obtain a delay circuit which does not involve an increase in a circuit area occupied by load transistors even when the number of inverters is increased, an integrated circuit device has four series-connected inverters 101 and two load transistors 104, 105, and is configured such that the A VDD...

20050280444 - System and method for balancing capacitively coupled signal lines: A signal balancing circuit for capacitively coupled signaling between transmitting and receiving devices over a plurality of capacitively coupled signal lines on which data signals are transmitted from the transmitting device to the receiving device. The signal balancing circuit includes an encode circuit for forcing a signal transition of a...

20050280445 - Pseudo cmos dynamic logic with delayed clocks: Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS logic gate includes a delayed enable clock transistor coupled to a source region...

20050275424 - Reducing electrical noise during bus turnaround in signal transfer systems: Systems and methods for reducing electrical noise generated during bus turnaround in signal transfer systems are provided. These systems include differential drivers having current sources continuously coupled to a signal bus during all operating modes of the drivers. A first transistor of the driver couples a first signal line of...

20050275425 - Memory system with a scheme capable of stably terminating a pair of differential signals transmitted via a pair of transmission lines: Provided is a memory system in which a pair of differential signals transmitted via a pair of transmission lines are prevented from being terminated at the same voltage during a standby mode, thereby preventing a receiver from entering an unstable state. The memory system includes a pair of transmission lines,...

20050275426 - Multiple-time programming apparatus and method using one-time programming element: A multiple-time programming apparatus and method using one-time programming (OTP) elements are provided. The apparatus comprises a first adjusting OTP element, a second adjusting OTP element and a logic device. An adjusting data is written into the first adjusting OTP element. When a modification in an IC is desired, the...

20050275427 - Field programmable gate array logic unit and its cluster: The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly...

20050275428 - Field programmable gate array logic unit and its cluster: The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly...

20050275429 - Single supply level shifter: A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal includes a first unit and a second unit. The first unit is connected to a high power supply voltage source and receives the input signal. The first unit acts as a startup...

20050275430 - Voltage level shifting circuit and method: A voltage level shifting circuit and method that can be used for shifting the voltage level of an input signal to provide an output signal having a higher output voltage level. The voltage level shifting circuit includes pull-up transistors that are switched OFF by the voltage of a pair of...

20050275431 - High-speed low-voltage differential signaling buffer using a level shifter: A low voltage differential signaling (LVDS) input buffer includes an NMOS differential amplifying circuit, a PMOS differential amplifying circuit, a first level-shift circuit for the NMOS differential amplifying circuit, a second level-shift circuit for the PMOS differential amplifying circuit and an output coupling circuit. The first level-shift circuit level-shifts a...

20050275432 - High voltage tolerant off chip driver circuit: An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the driver circuit in the active or...

20050270060 - A configurable integrated circuit for use in a multi-function handheld device: A configurable integrated circuit includes at least one general purpose input/output (GPIO) interface module, a first functional module, and a second functional module. The GPIO interface module includes a plurality of GPIO cells, wherein each of the GPIO cells is operably coupled to a corresponding pin of the configurable integrated...

20050270061 - Configurable logic circuit: A configurable logic circuit having a plurality of logic blocks and a connecting structure, via which the logic blocks are interconnectable, wherein the logic blocks are implemented in dual rail technique....

20050270063 - Method for portable plc configurations: Certain exemplary embodiments can comprise a method, comprising: recognizing, by a PLC, that a memory device has been connected to the PLC; and configuring the PLC via a PLC executable software program resident on the memory device. Certain exemplary embodiments can comprise a method, comprising: via a PLC network interface:...

20050270062 - System for portable plc configurations: Certain exemplary embodiments can comprise a method, comprising: recognizing, by a PLC, that a memory device has been connected to the PLC; and configuring the PLC via a PLC executable software program resident on the memory device. Certain exemplary embodiments can comprise a method, comprising: via a PLC network interface:...

20050270064 - Semiconductor device: An I/O buffer section is provided with a status setting circuit. The status setting circuit arbitrarily sets a signal state of an I/O terminal according to a combination of control signals stored in a setting register. Thus, the I/O buffer section is temporarily set to a Hi-Z state by the...

20050270065 - Coms buffer having higher and lower voltage operation: A buffer design for an integrated circuit that not only recognizes, but improves upon the skew problem as described above that is particularly problematic in cases where the output buffer supply voltage is particularly close or the same as the voltage of the signals coming from the core of an...

20050270066 - Level shifter and buffer circuit: A level shifter has a voltage converting circuit converting an input signal provided by a first power supply into an output signal provided by a second power supply, and a reset circuit outputting a reset signal when the first power supply is turned off. The voltage converting circuit has: first...

20050270068 - Circuits and methods for detecting and assisting wire transitions: A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a...

20050270069 - Repeater circuit having different operating and reset voltage ranges, and methods thereof: A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second...

20050270070 - Repeater circuit with high performance repeater mode and normal repeater mode: Repeater circuit with high performance repeater mode and normal repeater mode is provided and described. In one embodiment, switches are set to a first switch position to operate repeater circuit in the high performance repeater mode. In another embodiment, switches are set to a second switch position to operate the...

20050270067 - Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability: Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability, is provided and described. In one embodiment, switches are set to a first switch position to operate the repeater circuit in the high performance repeater mode. In another embodiment, switches...

20050264316 - Bus controller: A bus has two power consumption modes. A variable bus termination impedance is controlled to provide different bus termination impedances. A controller is coupled to the bus and includes a variable clock having different frequencies that are selectively provided to the controller. The impedance is increased or decreased responsive to...

20050264317 - Dynamic programmable logic array having enable unit: A DPLA (dynamic programmable logic array) uses an enable unit for each output line that provides OR-functionality, to eliminate a clock signal in the OR-plane. A clock signal is used only in the AND-plane for pre-charging the product term lines. Such a DPLA operates properly without a delay constraint between...

20050264318 - Redundancy structures and methods in a programmable logic device: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a...

20050264319 - Low voltage high-speed differential logic devices and method of use thereof: A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a combination XOR and latch, a multiplexer...

20050264320 - Logic circuits having linear and cellular gate transistors: A logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive...

20050264321 - Current mode logic buffer: Systems and methods provide current mode logic buffers and interface circuits. As an example, in accordance with an embodiment of the present invention, a CML buffer is disclosed that receives and/or provides multiple signal pairs having different common mode voltages to operate over a wider common mode voltage range....