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Electrical pulse counters, pulse dividers, or shift registers: circuits and systems October categorized by USPTO classification 10/12

20120269315 - Shift register: Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node... Agent:

20120269316 - Shift register: A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at... Agent:

20120257708 - Counting device and counting method: A counter counts the run lengths of a binarized signal. A counting result correcting portion generates frequency distributions for run lengths for first run lengths, which are from a rising edge to a falling edge of the signal, and second run lengths, which are for a falling edge to a... Agent: Yamatake Corporation

20120250815 - Method for determining usage rate of breaking hammer, breaking hammer, and measuring device: A method and measuring device for determining the usage rate of a breaking hammer, and to a rock breaking device. The measuring device comprises a sensor for measuring a physical phenomenon caused by the operation of the percussion device. The measuring results are processed, and they are used to determine... Agent:

20120250816 - Shift register of lcd devices: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The... Agent:

20120250817 - Vmos multi-valued counter unit: The present invention discloses a νMOS based multi-valued counter unit. The counter unit includes a νMOS source follower and at least a control gate connected the νMOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate.... Agent: Ningbo University