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Electrical pulse counters, pulse dividers, or shift registers: circuits and systems May archived by USPTO category 05/09

20090135991 - Pre-charge circuit and shift register with the same: A pre-charge circuit includes a receiving module, an enabling module, and a reset module. The receiving module receives the received driving signal of the pre-charge circuit and outputs the receiving driving signal according to a control signal. The enabling module outputs a pre-charge signal when receiving the driving signal. The... Agent: North America Intellectual Property Corporation

20090129534 - Semiconductor device, display device, and electronic device: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing... Agent: Fish & Richardson P.C.

20090129535 - Switch set of bi-directional shift register module: A switch set used in a bi-directional shift register circuit includes a plurality of switch devices. Each switch device is controlled by corresponding control signals to switch the direction of the input signal. One of the switch devices includes a first switch unit for transmitting a shift register signal from... Agent: North America Intellectual Property Corporation

20090122949 - System and method for wear leveling utilizing a relative wear counter: An invention is provided for wear leveling in a non-volatile memory system utilizing relative wear counters to indicate relative levels of wear for each memory block in a non-volatile memory system. Whenever a memory block is erased, the associated relative wear counter is incremented. Then, when any relative wear counter... Agent: Patent Venture Group

20090122950 - Afsm circuit and method for low jitter pll cmos programmable divider: A frequency divider (10A) includes an asynchronous finite state machine (AFSM) configured as a counter (20) having an input coupled to an input clock signal (CLK) for producing information representative of a plurality of phase signals (F0,F1,F2,F3) each of which is a divided-down representation of the input clock signal (CLK)... Agent: Texas Instruments Incorporated

20090122951 - Shift register circuit: A bidirectional shift register in which an operation margin is not lowered when a shift direction of a signal is switched is provided. A unit shift register SRk at one stage of a plurality of stages of shift registers includes a gate line drive unit, a forward shift unit, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090116610 - Low latency counter event indication: A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set... Agent: Scully, Scott, Murphy & Presser, P.C.

20090116611 - Space and power efficient hybrid counters array: A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid... Agent: Scully, Scott, Murphy & Presser, P.C.