Electrical pulse counters, pulse dividers, or shift registers: circuits and systems inventions 10/08

20080260089 - Quadrature divide-by-three frequency divider and low voltage muller c element: A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This frequency divider can be used in frequency synthesisers and as quadrature local oscillator generator.... Agent: Texas Instruments Incorporated

20080260090 - Shift register and shift registering apparatus: A shift register is provided for use in a data driver. The shift register includes a shift registering unit. The shift registering unit selectively receives a clock signal. The shift registering unit includes a flip-flop; and a first selection circuit. The first selection circuit selectively sends the clock signal to... Agent: Rabin & Berdo, PC

20080260089 - Quadrature divide-by-three frequency divider and low voltage muller c element: A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This frequency divider can be used in frequency synthesisers and as quadrature local oscillator generator.... Agent: Texas Instruments Incorporated

20080260090 - Shift register and shift registering apparatus: A shift register is provided for use in a data driver. The shift register includes a shift registering unit. The shift registering unit selectively receives a clock signal. The shift registering unit includes a flip-flop; and a first selection circuit. The first selection circuit selectively sends the clock signal to... Agent: Rabin & Berdo, PC

20080253498 - Electronic sensor with optimised counting capacity: counting means receiving the signal s, which are incremented with each pulse received, comprising a maximum counting capacity equal to z such that (b′−a′)≦z<a′, where z is a non-null natural integer, resetting the counting when the maximum counting capacity z is exceeded and outputting, at the end of the capture... Agent: Thelen Reid Brown Raysman & Steiner LLP

20080253499 - Shift register and level controller: A shift register includes several stages of shift register units. Each shift register unit includes a first level lifting unit, first level lowering unit, first driving unit and level controller. The first level lifting unit and first level lowering unit control the scan signal to be equal to a first... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080253500 - Flip-flop and shift register: A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for... Agent: Rabin & Berdo, PC

20080253501 - Shift register apparatus and shift register thereof: A shift register apparatus and a shift register thereof are provided. The shift register includes an input unit, a feedback unit, an output unit, and a reset unit. The shift register is made of MOS transistors, BJTs, or other switching transistors. In the present invention, an input signal is registered... Agent: J C Patents, Inc.

20080247500 - If counting method: In order to provide an IF counting method for realizing an IF counter with a smaller circuit configuration, an IF counter comprises a countdown IF counting unit 1 for counting frequency-divided IF signals, an IF count time period determination unit 2 for determining a count time period, an IF count... Agent: Woodcock Washburn LLP

20080247501 - Fifo register unit and method thereof: A FIFO register unit is provided, comprising a first sub-register unit, an input multiplexer and an output multiplexer. The first sub-register unit comprises a first register, a second register and a third register. The first register comprises an input terminal to receive a first input data. The second register receives... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP