Electrical pulse counters, pulse dividers, or shift registers: circuits and systems inventions 05/07

20070121777 - Methods to resolve tsf timer ambiguity of ieee 802.11e schedule element: A plurality of methods, computer program product, and apparatus that use a lower 32 bit field of a 64-bit 802.11 TSF timer, so as to encode the reference time instant without the ambiguity as to whether there the reference time is referring to a future time or a past time.... Agent: Philips Intellectual Property & Standards

20070104307 - Shift register: A shift register includes first and second stages for sequentially outputting scan pulses to drive first and second gate lines. One of the first and second stages includes a pull-up switching device connected to an enabling node of the one of the first and second stages; a first pull-down switching... Agent: Seyfarth Shaw, LLP