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Electrical fuse for silicon-on-insulator devicesRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Regenerative Type Switching Device (e.g., Scr, Comfet, Thyristor), Five Or More Layer Unidirectional StructureElectrical fuse for silicon-on-insulator devices description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060208274, Electrical fuse for silicon-on-insulator devices. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a divisional of patent application Ser. No. 10/811,405, entitled "Method of Fabricating an Electrical Fuse for Silicon-On-Insulator Devices," filed on Mar. 26, 2006, which application is incorporated herein by reference. TECHNICAL FIELD [0002] The present invention relates to semiconductor devices and, in particular, to an electrical fuse for silicon-on-insulator devices. BACKGROUND [0003] Fuses are commonly used in integrated circuits to provide redundancy and programming capabilities. To increase yield in integrated circuits such as memory chips, it is common to include redundant memory cells on the memory chips. If a memory circuit is found to be defective or is not needed, the fuse may be blown by activating or deactivating the redundant memory cells. Another common practice is to utilize fuses to program or customize integrated circuits for a particular application or customer. In this manner, the same chip may be produced and customized for individual customers by programming the fuses after fabrication, thereby reducing the fabrication costs. [0004] Typically, fuses comprise a conductive link that may be blown or ruptured to prevent current from flowing. The conductive link is typically formed of a metal, such as aluminum or copper, and blown by a laser. The use of the laser, however, requires complicated processing steps and expensive laser equipment. [0005] Another type of fuse involves the use of an electrical fuse. Generally, an electrical fuse comprises two endpoints or contact pads connected with a thinner link, referred to as a fuse link. The electrical fuse is formed from a layer of polysilicon that has been deposited on a silicon substrate and silicided. In operation, the smaller dimensions of the fuse link causes high current concentrations or "current crowding" where the dimensions of the fuse are reduced in the fuse link. To program or "blow" the fuse, an electrical current of sufficient magnitude is passed through the fuse link for a sufficient period of time to cause silicide agglomeration or melting of the fuse link, thereby increasing the resistance of the link. A sensing circuit is then able to sense the amount of resistance to determine the state of the fuse. [0006] In recent years, silicon-on-insulator (SOI) substrates have been investigated for use in semiconductor processing. As the use of SOI substrates increases, it is necessary to develop new process steps and devices to incorporate aspects of the SOI substrates. In particular, new processes are needed to incorporate the use and fabrication of an electrical fuse into existing SOI fabrication processes. For the processes to be effective and useful, the processes should be integrated with existing processes, adding no or few additional process steps. BRIEF SUMMARY OF THE INVENTION [0007] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which provides an electrical fuse for silicon-on-insulator devices. [0008] In accordance with a preferred embodiment of the present invention, a method for fabricating an electrical fuse on an SOI substrate is provided. The active layer of the SOI substrate is patterned such that an electrical fuse is formed. The surface of the active layer is silicided. [0009] In accordance with another preferred embodiment of the present invention, a method of forming a semiconductor device is provided. The method includes providing an SOI substrate having an active layer formed on an insulator layer. A source/drain region of a transistor and an electrical fuse are simultaneously patterned in the active layer. A gate electrode is formed over the source/drain regions and lightly-doped drains are formed. An ion implant process is performed to dope the electrical fuse and the source/drain region. [0010] In accordance with yet another embodiment of the present invention, an electrical fuse formed on an SOI wafer is provided. The electrical fuse has a first section and a second section interconnected by a third section. The first, second, and third sections are formed from the active layer of the SOI wafer. The surface of the electrical fuse may be silicided. [0011] In accordance with yet still another embodiment of the present invention, a semiconductor device is provided. The semiconductor device comprises a source/drain region of a transistor and an electrical fuse formed in an active layer of an SOI. [0012] An advantage of the present invention is that it provides an electrical fuse formed from the active layer of an SOI wafer. The fabrication of the electrical fuse may be incorporated into standard processing techniques for SOI wafers and adds no or few additional process steps. Thus, the present invention provides an efficient and cost effective manner of providing an electrical fuse on an SOI wafer. [0013] The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0014] The above features of the present invention will be more clearly understood from consideration of the following descriptions in connection with the accompanying drawings in which: [0015] FIGS. 1, 2a, 2b, 3a, 3b, 4a, 4b, 5a, 5b, 6a, 6b, 7a, and 7b are cross-section side views illustrating various steps of fabricating an electrical fuse in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS [0016] The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. [0017] Referring now to the drawings, wherein like reference numerals are used herein to designate like elements throughout the various views, preferred embodiments of the present invention are illustrated and described. As will be understood by one of ordinary skill in the art, the figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many applications and variations of the present invention in light of the following description for preferred embodiments of the present invention. The preferred embodiments discussed herein are just a few illustrative examples of the present invention and do not necessarily limit the scope of the invention to the preferred embodiments described. [0018] In the discussion that follows, a method of forming an electrical fuse on an SOI substrate is provided. The method is integrated with known process steps to fabricate a transistor such that the electrical fuse and a transistor are formed simultaneously. It should be noted that the formation of the electrical fuse does not require additional process steps. Rather, the masks are altered such that the electrical fuse and the transistor may be formed simultaneously without additional process steps. It should also be noted, however, that a transistor is used for illustrative purposes only and that embodiments of the present invention may be used to fabricate an electrical fuse simultaneously with other semiconductor devices with no or few additional process steps. For example, embodiments of the present invention may be used to fabricate an electrical fuse simultaneously as fin-field effect transistors (FinFETs), capacitors, and the like. [0019] Referring now to FIG. 1, a cross-section view is shown of an SOI wafer 100. Generally, SOI substrates, such as SOI wafer 100, have an active layer 110, an insulator layer 112, and a substrate 114. The active layer 110, generally formed of a thin epitaxial layer of silicon, silicon-germanium oxide, germanium, strained silicon, or the like, is disposed on the insulator layer 112. The insulator layer 112, often referred to as a buried oxide (BOX) layer, is provided on the substrate 114, which is typically a silicon or glass substrate. The insulator layer 112 is comprised of an insulator such as silicon dioxide, which electrically isolates the active layer 110 from the substrate 114. Continue reading about Electrical fuse for silicon-on-insulator devices... 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