|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/27/2014 > 13 patent applications in 11 patent subcategories.
20140059322 - Apparatus and method for broadcasting from a general purpose register to a vector register: An apparatus and method are described for broadcasting from a general purpose source register to a destination vector register. For example, a method according to one embodiment includes the following operations: selecting data element position N within the destination vector register to be updated; broadcasting a set of data from... Agent:
20140059323 - Systems and methods of data extraction in a vector processor: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source... Agent: Qualcomm Incorporated
20140059324 - System core for transferring data between an external device and memory: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the... Agent:
20140059325 - Integrated circuit apparatus, three-dimensional integrated circuit, three-dimensional processor device, and process scheduler, with configuration taking account of heat: The present invention provides a three-dimensional integrated circuit wherein generation of hot spot which makes a high temperature part as a result of intensively generated heat can be suppressed in. The integrated circuit apparatus comprises: a first circuit made of a memory circuit, a second circuit made of an arithmetic... Agent: Panasonic Corporation
20140059326 - Calculation processing device and calculation processing device controlling method: A calculation-processing-device includes: a decoder unit including, a first-counter to increment a first-count-value and to decrement the-first-count-value, and a second-counter configured to increment a second-count-value and to decrement the second-count-value; a first-instruction-executing-unit to execute an instruction of the first-class; a second-instruction-executing-unit to execute an instruction of the-second class; a first-instruction... Agent:
20140059327 - Detecting cross-talk on processor links: A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a... Agent: International Business Machines Corporation
20140059328 - Mechanism for performing speculative predicated instructions: A mechanism for executing speculative predicated instructions may include execution of initiating execution of a vector instruction when one or more operands upon which the vector instruction depends are available for use, even if a predicate vector that the vector instruction also depends is not available. If the predicate vector... Agent:
20140059329 - Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions: A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an... Agent: International Business Machines Corporation
20140059330 - Parsing-enhancement facility: An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general registers, wherein a first general register stores an... Agent: International Business Machines Corporation
20140059331 - Branch target buffer for emulation environments: Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a... Agent: International Business Machines Corporation
20140059332 - Branch target buffer for emulation environments: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch... Agent: International Business Machines Corporation
20140059334 - Autonomic hotspot profiling using paired performance sampling: A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular... Agent: International Business Machines Corporation
20140059333 - Method, apparatus, and system for speculative abort control mechanisms: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And... Agent:02/20/2014 > 14 patent applications in 10 patent subcategories.
20140052959 - Experimental engineering optimization algorithm at point of performance: A method is provided for reducing the data set used in creating an optimization algorithm, thus to permit the use of microprocessors, that in turn permits embedding the optimization algorithm at the point of performance, in which a subset of data points in a performance window is used to derive... Agent: Bae Systems Information And Electronic Systems Integration, Inc.
20140052960 - Apparatus and method for generating vliw, and processor and method for processing vliw: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a... Agent: Samsung Electronics Co., Ltd.
20140052961 - Parallel memory systems: The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core,... Agent:
20140052962 - Custom chaining stubs for instruction code translation: A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction... Agent: Nvidia Corporation
20140052963 - Technique to perform three-source operations: A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than two source values.... Agent:
20140052964 - Programmable logic unit and method for translating and processing instructions using interpretation registers: An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of... Agent: 3dlabs Inc., Ltd.
20140052965 - Dynamic cpu gpu load balancing using power: Dynamic CPU GPU load balancing is described based on power. In one example, an instruction is received and power values are received for a central processing core (CPU) and a graphics processing core (GPU). The CPU or the GPU is selected based on the received power values and the instruction... Agent:
20140052966 - Mechanism for consistent core hang detection in a processor core: Mechanism for consistent core hang detection on a processor with multiple processor cores, each having one or more instruction execution pipelines. Each core may also include a hang detection unit with a counter unit that may generate a count value based on a clock source having a frequency that is... Agent:
20140052967 - Method and apparatus for dynamic data configuration: A method and apparatus for configuring dynamic data are provided. A compilation apparatus may select a data format showing an optimum performance when a binary code is executed, from among a plurality of data formats supported by an execution apparatus used to execute a binary code, and may generate a... Agent: Samsung Electronics Co., Ltd.
20140052970 - Opcode counting for performance measurement: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight... Agent: International Business Machines Corporation
20140052968 - Super multiply add (super madd) instruction: A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second... Agent: Intel Corporation
20140052969 - Super multiply add (super madd) instructions with three scalar terms: A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The... Agent: Intel Corporation
20140052971 - Native code instruction selection: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for selecting native code instructions. One of the methods includes receiving an initial machine language instruction for execution by a processor in a first execution mode; determining that a portion of the initial machine language instruction, when executed... Agent:
20140052972 - Meta predictor restoration upon detecting misprediction: Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was... Agent: Micron Technology, Inc.02/13/2014 > 13 patent applications in 9 patent subcategories.
20140047211 - Vector register file: An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a... Agent: International Business Machines Corporation
20140047212 - Semiconductor device: A semiconductor device of the present invention has processor elements each of which divides data that is contiguous in one direction into multiple data groups and processes them, a processor element control unit that issues a data shift instruction, and a data transfer network that performs data transfer between adjacent... Agent: Renesas Electronics Corporation
20140047213 - Method and system for memory overlays for portable function pointers: A system and method for implementing memory overlays for portable pointer variables. The method includes providing a program executable by a heterogeneous processing system comprising a plurality of a processors running a plurality of instruction set architectures (ISAs). The method also includes providing a plurality of processor specific functions associated... Agent: Nvidia Corporation
20140047216 - Scalable decode-time instruction sequence optimization of dependent instructions: Producer-consumer instructions, comprising a first instruction and a second instruction in program order, are fetched requiring in-order execution, the second instruction is modified by the processor so that the first instruction and second instruction can be completed out-of-order, the modification comprising any one of extending an immediate field of the... Agent: International Business Machines Corporation
20140047215 - Stall reducing method, device and program for pipeline of processor with simultaneous multithreading function: The disclosure provides a technique for suppressing the occurrence of stalling caused by data dependency other than register dependency in an out-of-order processor. A stall reducing program includes a handler for detecting a stall occurring during execution of execution code using a PMU, and identifying, based on dependencies, a second... Agent: International Business Machines Corporation
20140047214 - Vector register file: An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a... Agent: International Business Machines Corporation
20140047217 - Satisfiability checking: A satisfiability checking system may include a single instruction, multiple data (SIMD) machine configured to execute multiple threads in parallel. The multiple threads may be divided among multiple blocks. The SIMD machine may be further configured to perform satisfiability checking of a formula including multiple parts. The satisfiability checking may... Agent: Fujitsu Limited
20140047219 - Managing a register cache based on an architected computer instruction set having operand last-user information: A multi-level register hierarchy is disclosed comprising a first level pool of registers for caching registers of a second level pool of registers in a system wherein programs can dynamically release and re-enable architected registers such that released architected registers need not be maintained by the processor, the processor accessing... Agent: International Business Machines Corporation
20140047218 - Multi-stage register renaming using dependency removal: Multi-stage register renaming using dependency removal is described. In an embodiment, the registers are renamed in two stages. The first stage involves removing all the dependencies within a set of instructions which are being renamed together. The final stage then renames all registers in parallel using a renaming map. In... Agent: Imagination Technologies Limited
20140047220 - Residual addition for video software techniques: According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing a plurality of unpacked data operands, adding a plurality... Agent:
20140047221 - Fusing flag-producing and flag-consuming instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media: Fusing flag-producing and flag-consuming instructions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a flag-producing instruction indicating a first operation generating a first flag result is detected in an instruction stream by an instruction processing circuit. The instruction processing circuit also... Agent: Qualcomm Incorporated
20140047222 - Method and device for recombining runtime instruction: A method for recombining runtime instruction comprising: an instruction running environment is buffered; the machine instruction segment to be scheduled is obtained; the second jump instruction which directs an entry address of an instruction recombining platform is inserted before the last instruction of the obtained machine instruction segment to generate... Agent: Beijing Zhongtian Antai Technology Co., Ltd.
20140047223 - Selectively activating a resume check operation in a multi-threaded processing system: This disclosure describes techniques for selectively activating a resume check operation in a single instruction, multiple data (SIMD) processing system. A processor is described that is configured to selectively enable or disable a resume check operation for a particular instruction based on information included in the instruction that indicates whether... Agent:02/06/2014 > 11 patent applications in 6 patent subcategories.
20140040594 - Programmable device for software defined radio terminal: A programmable device suitable for software defined radio terminal is disclosed. In one aspect, the device includes a scalar cluster providing a scalar data path and a scalar register file and arranged for executing scalar instructions. The device may further include at least two interconnected vector clusters connected with the... Agent: Imec
20140040595 - Space efficient checkpoint facility and technique for processor with integrally indexed register mapping and free-list arrays: A processor may efficiently implement register renaming and checkpoint repair even in instruction set architectures with large numbers of wide (bit-width) registers by (i) renaming all destination operand register targets, (ii) implementing free list and architectural-to-physical mapping table as a combined array storage with unitary (or common) read, write and... Agent: Freescale Semiconductor, Inc.
20140040600 - Data processor: In the data processor in which a combination of multiple specific instructions is prohibited, an instruction set is employed that additionally defines that prohibition combination pattern as a separate instruction. With respect to the prohibition combination pattern additionally defined as the separate instruction, for example, in order to make a... Agent: Renesaselectronics Corporation
20140040596 - Packed load/store with gather/scatter: Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers... Agent: International Business Machines Corporation
20140040599 - Packed load/store with gather/scatter: Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an... Agent: International Business Machines Corporation
20140040597 - Predication in a vector processor: Embodiments relate to vector processor predication in an active memory device. An aspect includes a system for vector processor predication in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform... Agent: International Business Machines Corporation
20140040598 - Vector processing in an active memory device: Embodiments relate to vector processing in an active memory device. An aspect includes a system for vector processing in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method... Agent: International Business Machines Corporation
20140040601 - Predication in a vector processor: Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in... Agent: International Business Machines Corporation
20140040602 - Storage method, memory, and storing system with accumulated write feature: A storage method, a memory and a storage system that have an accumulated write feature are provided in which the OR and AND operation are shifted from CPU/ALU (controller) to the memory, and the frequency for switching data transmission lines between read and write instructions can be reduced. In the... Agent: Xi'an Sinochip Semiconductors Co., Ltd.
20140040603 - Vector processing in an active memory device: Embodiments relate to vector processing in an active memory device. An aspect includes a method for vector processing in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. An... Agent: International Business Machines Corporation
20140040604 - Packed rotate processors, methods, systems, and instructions: A method of an aspect includes receiving a masked packed rotate instruction. The instruction indicates a first source packed data including a plurality of packed data elements, a packed data operation mask having a plurality of mask elements, at least one rotation amount, and a destination storage location. A result... Agent:Previous industry: Electrical computers and digital processing systems: memory
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