|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/10/2014 > 9 patent applications in 9 patent subcategories.
20140101410 - Method and system for managing hardware resources to implement system functions using an adaptive computing architecture: An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a... Agent: Altera Corporation
20140101411 - Dynamically switching a workload between heterogeneous cores of a processor: In one embodiment, a policy manager may receive operating system scheduling information, performance prediction information for at least one future quantum, and current processor utilization information, and determine a performance prediction for a future quantum and whether to cause a switch between asymmetric cores of a multicore processor based at... Agent:
20140101412 - Speculative privilege elevation: Systems and methods are provided for speculatively elevating a privilege level at which instructions are executed. In embodiment, this is accomplished b identification of a privilege elevation instruction (e.g., SYSCALL) at an early pipeline stage and speculatively executing subsequent instructions with elevated privileges.... Agent:
20140101413 - Information handling system including hardware and software prefetch: A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the... Agent: International Business Machines Corporation
20140101414 - Technique for translating dependent instructions: In response to determining an operation is a dependent operation, a mapper of a processor determines the source registers of the operation from which the dependent operation depends. The mapper translates the dependent operation to a new operation that uses as its source operands at least one of the determined... Agent: Advanced Micro Devices, Inc.
20140101415 - Reducing data hazards in pipelined processors to provide high processor utilization: A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions... Agent: Micron Technology, Inc.
20140101416 - Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall: During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of... Agent: International Business Machines Corporation
20140101417 - Code coverage framework: An information processing system records an execution of a program instruction. A determination is made that a thread has entered a program unit. Another determination is made that that the thread is associated with at least one attribute that matches a set of thread recording criteria. An instruction recording mechanism... Agent: International Business Machines Corporation
20140101418 - Mitigating instruction prediction latency with independently filtered presence predictors: Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction... Agent: International Business Machines Corporation04/03/2014 > 24 patent applications in 15 patent subcategories.
20140095828 - Vector move instruction controlled by read and write masks: A processor executes a vector move instruction to move data elements from a second vector register to a first vector register under the control of a first mask register and a second mask register. A register file within the processor includes the first vector register, the second vector register, the... Agent:
20140095829 - Method and device for passing parameters between processors: The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the... Agent: Zte Corporation
20140095830 - Instruction for shifting bits left with pulling ones into less significant bits: A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data elements of an array. The processor further includes execution circuitry to receive a mask generating instruction that specifies at... Agent:
20140095831 - Apparatus and method for efficient gather and scatter operations: An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations... Agent:
20140095832 - Method and apparatus for performance efficient isa virtualization using dynamic partial binary translation: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set.... Agent:
20140095833 - Prefix computer instruction for compatibly extending instruction functionality: A prefix instruction is executed and passes operands to a next instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a... Agent: International Business Machines Corporation
20140095834 - Instruction and logic for boyer-moore search of text strings: Instructions and logic provide extended vector suffix comparisons for Boyer-Moore searches. Some embodiments, responsive to an instruction specifying: a pattern source operand and a target source operand, compare each of m data elements of the pattern operand with each data element of the target operand. A first and second equal... Agent:
20140095835 - Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching: A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response... Agent: International Business Machines Corporation
20140095836 - Cross-pipe serialization for multi-pipeline processor: Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first... Agent: International Business Machines Corporation
20140095840 - Diagnose instruction for serializing processing: A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a... Agent: International Business Machines Corporation
20140095839 - Monitoring processing time in a shared pipeline: A pipelined processing device includes: a pipeline controller configured to receive at least one instruction associated with an operation from each of a plurality of subcontrollers, and input the at least one instruction into a pipeline; and a pipeline counter configured to receive an active time value from each of... Agent: International Business Machines Corporation
20140095838 - Physical reference list for tracking physical register sharing: A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of... Agent:
20140095841 - Processor and control method of processor: A processor including a circuit unit includes a state information holding unit, a direction controller, a direction generator, and a direction execution unit. The state information holding unit holds state information indicating a state of the circuit unit. The direction controller decodes a first direction for generating a control direction... Agent: Fujitsu Limited
20140095837 - Read and write masks update instruction for vectorization of recursive computations over interdependent data: A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor includes the first mask register and the second mask register. The processor includes execution circuitry to execute the mask update instruction. In response to... Agent:
20140095842 - Accelerated interlane vector reduction instructions: A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution... Agent:
20140095843 - Systems, apparatuses, and methods for performing conflict detection and broadcasting contents of a register to data element positions of another register: Systems, apparatuses, and methods of performing in a computer processor broadcasting data in response to a single vector packed broadcasting instruction that includes a source writemask register operand, a destination vector register operand, and an opcode. In some embodiments, the data of the source writemask register is zero extended prior... Agent:
20140095845 - Apparatus and method for efficiently executing boolean functions: An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to... Agent:
20140095844 - Systems, apparatuses, and methods for performing rotate and xor in response to a single instruction: Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.... Agent:
20140095846 - Trace based measurement architecture: A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and enabling a parallel trace mode multiplexer to output all trace data, representing all data writes to the local memory, to a single observation unit.... Agent: Infineon Technologies Ag
20140095847 - Instruction and highly efficient micro-architecture to enable instant context switch for user-level threading: A processor uses multiple banks of an extended register set to store the contexts of multiple user-level threads. A current bank register provides a pointer to the bank that is currently active. A first thread saves its context (first context) in a first bank of the extended register set and... Agent:
20140095848 - Tracking operand liveliness information in a computer system and performing function based on the liveliness information: Operand liveness state information is maintained during context switches for current architected operands of executing programs the current operand state information indicating whether corresponding current operands are any one of enabled or disabled for use by a first program module, the first program module comprising machine instructions of an instruction... Agent: International Business Machines Corporation
20140095849 - Instruction and logic for optimization level aware branch prediction: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then... Agent:
20140095850 - Loop vectorization methods and apparatus: Loop vectorization methods and apparatus are disclosed. An example method includes generating a first control mask for a set of iterations of a loop by evaluating a condition of the loop, wherein generating the first control mask includes setting a bit of the control mask to a first value when... Agent:
20140095851 - Delaying interrupts for a transactional-execution facility: A mechanism is provided for completing of set of instructions while receiving interrupts. The mechanism executes a set of instructions. Responsive to receiving an interrupt and determining that the interrupt requires processing within an implementation time frame, the mechanism delays the interrupt for a predetermined time period. Responsive to completing... Agent: International Business Machines Corporation03/27/2014 > 14 patent applications in 11 patent subcategories.
20140089634 - Apparatus and method for detecting identical elements within a vector register: An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector... Agent:
20140089635 - Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the... Agent:
20140089636 - Caching optimized internal instructions in loop buffer: Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be... Agent: International Business Machines Corporation
20140089637 - Optimizing system throughput by automatically altering thread co-execution based on operating system directives: A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by... Agent: International Business Machines Corporation
20140089638 - Multi-destination instruction handling: Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline... Agent: Apple Inc.
20140089639 - Processor with instruction concatenation: A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction.... Agent: Texas Instruments Incorporated
20140089642 - Methods and systems for performing a replay execution: One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine... Agent:
20140089641 - Processor with instruction iteration: A processor includes a plurality of execution units. At least one of the execution units is configured to repeatedly execute a first instruction based on a first field of the first instruction indicating that the first instruction is to be iteratively executed.... Agent: Texas Instruments Incorporated
20140089640 - Processor with variable instruction atomicity: A processor includes a plurality of execution units. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute, and to enforce atomic execution of the complex instruction during a first-portion of the multiple instruction cycles required to execute the... Agent: Texas Instruments Incorporated
20140089643 - Information processing apparatus and instruction offloading method: In general, according to one embodiment, an information processing apparatus includes an issuer and a communicator. The issuer issues an offload instruction corresponding to a first process executed in company with a first identifier capable of uniquely specifying a resource of a first arithmetic operation device. The communicator transmits the... Agent: Kabushiki Kaisha Toshiba
20140089644 - Circuit and method for identifying exception cases in a floating-point unit and graphics processing unit employing the same: A floating-point unit and a method of identifying exception cases in a floating-point unit. In one embodiment, the floating-point unit includes: (1) a floating-point computation circuit having a normal path and an exception path and operable to execute an operation on an operand and (2) a decision circuit associated with... Agent: Nvidia Corporation
20140089645 - Processor with execution unit interoperation: A processor includes a plurality of execution units. Each of the execution units includes processing logic configured to process data, and registers accessible by the processing logic. At least one of the execution units is configured to execute a first instruction that causes the at least one execution unit to:... Agent: Texas Instruments Incorporated
20140089646 - Processor with interruptable instruction execution: A processor includes a plurality of execution units. Each of the execution units includes a status register configured to store a value indicative of state of the execution unit. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute.... Agent: Texas Instruments Incorporated
20140089647 - Branch predictor for wide issue, arbitrarily aligned fetch: In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where... Agent:03/20/2014 > 16 patent applications in 13 patent subcategories.
20140082325 - Intelligent architecture creator: Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of... Agent:
20140082326 - Vehicle electronic controller: Some embodiments relate to a vehicle electronic controller having a microcomputer and a port expansion element, with reduced power consumption and radio noise. An MCU (microcomputer) performs determination processing that determines whether an output condition is established that is based on a signal that is input via a signal input... Agent: Sumitomo Wiring Systems, Ltd.
20140082327 - Continuous run-time validation of program execution: a practical approach: Trustworthy systems require that code be validated as genuine. Most systems implement this requirement prior to execution by matching a cryptographic hash of the binary file against a reference hash value, leaving the code vulnerable to run time compromises, such as code injection, return and jump-oriented programming, and illegal linking... Agent: The Research Foundation Of State University Of New York
20140082329 - Continuous run-time validation of program execution: a practical approach: Trustworthy systems require that code be validated as genuine. Most systems implement this requirement prior to execution by matching a cryptographic hash of the binary file against a reference hash value, leaving the code vulnerable to run time compromises, such as code injection, return and jump-oriented programming, and illegal linking... Agent: The Research Foundation Of State University Of New York
20140082328 - Method and apparatus to process 4-operand simd integer multiply-accumulate instruction: According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value;... Agent: Intel Corporation
20140082330 - Enhanced instruction scheduling during compilation of high level source code for improved executable code: Systems and methods for static code scheduling are disclosed. A method can include receiving an intermediate representation of source code, building a directed acyclic graph (DAG) for the intermediate representation, and creating chains of dependent instructions from the DAG for cluster formation. The chains are merged into clusters and each... Agent: Qualcomm Innovation Center, Inc.
20140082331 - System and method for synchronizing processor instruction execution: A system and method for controlling processor instruction execution. In one example, a method for synchronizing a number of instructions performed by processors includes instructing a first processor to iteratively execute instructions via a first set of iterations until a predetermined time period has elapsed. A number of instructions executed... Agent: General Electric Company
20140082332 - Semiconductor integrated circuit and compiler: A semiconductor integrated circuit includes: a floating point arithmetic unit that includes circuit resources over which power saving control is performed, and executes a floating point arithmetic operation; a power-control instruction control unit that receives a pre-access instruction corresponding to a floating point arithmetic operation instruction, and invalidates stepwise the... Agent: Fujitsu Limited
20140082333 - Systems, apparatuses, and methods for performing an absolute difference calculation between corresponding packed data elements of two vector registers: Embodiments of systems, apparatuses, and methods for performing in a computer processor absolute difference calculation in response to a single vector packed absolute difference instruction that includes a first and second source vector register operand, a destination vector register operand, and an opcode are described.... Agent:
20140082334 - Encoding to increase instruction set density: A conventional instruction set architecture such, as the x86 instruction set architecture, may be reencoded to reduce the amount of memory used by the instructions. This may be particularly useful in applications that are memory sized limited, as is the case with microcontrollers. With a reencoded instruction set that is... Agent:
20140082335 - Characterization and validation of processor links: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One... Agent: International Business Machines Corporation
20140082337 - Branch target buffer preload table: Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table... Agent: International Business Machines Corporation
20140082336 - Target buffer address region tracking: Embodiments relate to target buffer address region tracking. An aspect includes receiving a restart address, and comparing, by a processing circuit, the restart address to a first stored address and to a second stored address. The processing circuit determines which of the first and second stored addresses is identified as... Agent: International Business Machines Corporation
20140082338 - Instruction filtering: Embodiments relate to instruction filtering. An aspect includes a computer-implemented method for instruction filtering. The method includes detecting, by a processor, a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in a tracking array based on detecting and executing the tracked instruction. The... Agent: International Business Machines Corporation
20140082339 - Global weak pattern history table filtering: Embodiments relate to global weak pattern history table (PHT) filtering. An aspect includes receiving a search address associated with a branch prediction, and receiving a prediction strength indicator and a tag from a PHT. Based on determining that the tag matches the search address and the prediction strength indicator is... Agent: International Business Machines Corporation
20140082340 - System and method for controlling processor instruction execution: A system and method for controlling processor instruction execution. In one example, a method for controlling a total number of instructions executed by a processor includes instructing the processor to iteratively execute instructions via multiple iterations until a predetermined time period has elapsed. A number of instructions executed in each... Agent: General Electric CompanyPrevious industry: Electrical computers and digital processing systems: memory
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