|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 12/05/2013 > 15 patent applications in 11 patent subcategories.
20130326190 - Coarse-grained reconfigurable processor and code decompression method thereof: A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header... Agent: Samsung Electronics Co., Ltd.
20130326191 - System and method for distributed computing: The invention refers to tightly coupled multiprocessor distributed computing systems. The proposed solution enables to develop distributed applications as usual monolithic applications with use of typical compilers and builders. These applications support complicated logic of interaction between elements executed in different nodes and, at that, have limited complexity of development.... Agent:
20130326192 - Broadcast operation on mask register: Embodiments of systems, apparatuses, and methods for performing a mask broadcast instruction in a computer processor are described. In some embodiments, the execution of a mask broadcast instruction causes a broadcast of a data element of the source operand to a destination register of the destination operand according to the... Agent:
20130326193 - Processor resource and execution protection methods and apparatus: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege... Agent:
20130326194 - Method, apparatus and instructions for parallel data conversions: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first... Agent:
20130326195 - Preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable media: Preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable media are disclosed. In this regard, a method for processing instructions in a central processing unit (CPU) is provided. The method comprises decoding an instruction comprising a plurality of bits, and generating a parity error indicator indicating... Agent: Qualcomm Incorporated
20130326196 - Systems, apparatuses, and methods for performing vector packed unary decoding using masks: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed unary value decoding using masks in response to a single vector packed unary decoding using masks instruction that includes a destination vector register operand, a source writemask register operand, and an opcode are described.... Agent:
20130326197 - Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media: Issuing instructions to execution pipelines based on register-associated preferences and related instruction processing circuits, systems, methods, and computer-readable media are disclosed. In one embodiment, an instruction is detected in an instruction stream. Upon determining that the instruction specifies at least one source register, an execution pipeline preference(s) is determined based... Agent: Qualcomm Incorporated
20130326198 - Load-store dependency predictor pc hashing: Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and... Agent:
20130326199 - Method and apparatus for controlling a mxcsr: Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may... Agent:
20130326200 - Integrated circuit devices and methods for scheduling and executing a restricted load operation: An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation... Agent: Freescale Semiconductor, Inc.
20130326201 - Processor-based apparatus and method for processing bit streams: An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving... Agent:
20130326202 - Load test capacity planning: Disclosed herein are techniques for load test capacity planning. Resources consumed by instructions executing in a first computer apparatus are determined. A metric associated with a second computer apparatus is determined. A number of instances of the instructions that are able to execute concurrently in the second computer apparatus is... Agent:
20130326203 - Multiprocessor: A microprocessor has a plurality of debug modules, multiple sets of processor cores provided corresponding to the debug modules so that each set of the processor cores are debugged by the corresponding debug module, and a plurality of debug ring units provided corresponding to the debug modules, each debug ring... Agent: Kabushiki Kaisha Toshiba
20130326204 - Configuration-preserving preprocessor and configuration-preserving parser: Methods, systems, and apparatuses, including computer programs encoded on computer readable media, for generating a plurality of tokens from one or more source files that include source code in a first programming language. The source code includes one or more static conditionals that include a conditional expression and branch code... Agent: New York University11/28/2013 > 11 patent applications in 8 patent subcategories.
20130318324 - Minicore-based reconfigurable processor and method of flexibly processing multiple data using the same: A minicore-based reconfigurable processor and a method of flexibly processing multiple data using the same are provided. The reconfigurable processor includes minicores, each of the minicores including function units configured to perform different operations, respectively. The reconfigurable processor further includes a processing unit configured to activate two or more function... Agent: Samsung Electronics Co., Ltd.
20130318325 - Composite processors: In one example, a composite processor (100) includes a circuit board (1200), a first processor element package (1230), and a second processor element package (1240). The circuit board has an optical link (1211) and an electrical link (1221). The first processor element package (1230) includes a substrate (1231) with an... Agent:
20130318326 - Self-similar processing network: Self-similar processing by unit processing cells may together solve a problem. A unit processing cell may include a processor, a memory and a plurality of Input/Output (IO) channels coupled to the processor. The memory may include a dictionary having one or more instructions that configure the processor to perform at... Agent:
20130318328 - Apparatus and method for shuffling floating point or integer values: An apparatus and method are described for shuffling data elements from source registers to a destination register. For example, a method according to one embodiment includes the following operations: reading each mask bit stored in a mask data structure, the mask data structure containing mask bits associated with data elements... Agent:
20130318327 - Method and apparatus for data processing: A method for processing an operating sequence of instructions of a program in a processor, wherein each instruction is represented by an assigned instruction code which comprises one execution step to be processed by the processor or a plurality of execution steps to be processed successively by the processor, includes... Agent: Infineon Technologies Ag
20130318329 - Co-processor for complex arithmetic processing, and processor system: In order to enable to quickly and efficiently execute, by one system, various modulation/demodulation/synchronous processes in a plurality of radio communication methods, a co-processor (22) for complex arithmetic processing, which forms a processor system (100), includes a complex arithmetic circuit (22) that executes for complex data a complex arithmetic operation... Agent: Nec Corporation
20130318330 - Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors: A method and information processing system manage load and store operations that can be executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard... Agent: International Business Machines Corporation
20130318331 - Start control apparatus, information device, and start control method: A CPU includes a code write unit which writes an interrupt generation code into a page in which the instructions stored in the non-volatile memory are not written, among a plurality of the pages included in an instruction area that is an area of the volatile memory into which the... Agent: Panasonic Corporation
20130318332 - Branch misprediction behavior suppression using a branch optional instruction: A method for suppressing branch misprediction behavior is contemplated in which a branch-optional instruction that would cause the flow of control to branch around instructions in response to a determination that a predicate vector is null is predicted not taken. However, in response to detecting that the prediction is incorrect,... Agent:
20130318334 - Dynamic interrupt reconfiguration for effective power management: Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a... Agent:
20130318333 - Operating processors over a network: A client processor can save an execution state of a process that runs on two or more secondary processors in a single file. The single file can be transferred from the client processor over a network to a host processor. The single file is configured to permit the host processor... Agent:11/21/2013 > 10 patent applications in 8 patent subcategories.
20130311751 - System and data loading method: A system includes plural processors; memory that stores a program currently under execution by the processors; and a pre-loader that pre-loads into a fragment area of the memory, a target program that is to be executed and is a program other than the program currently under execution by the processors.... Agent: Fujitsu Limited
20130311752 - Instruction-optimizing processor with branch-count table in hardware: A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic... Agent: Nvidia Corporation
20130311753 - Method and device (universal multifunction accelerator) for accelerating computations by parallel computations of middle stratum operations: This invention constitutes a method and apparatus for enabling parallel computations of intermediate operations which are generic in many algorithms in given applications and also contain most of the computationally intensive operations. The method includes designing a set of intermediate level functions suitable for predefined application, obtaining instructions corresponding to... Agent:
20130311754 - Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit.... Agent: Qualcomm Incorporated
20130311756 - Rotate instructions that complete execution without reading carry flag: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution... Agent:
20130311755 - Running state power saving via reduced instructions per clock operation: A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial... Agent: Via Technologies, Inc.
20130311757 - Extract cpu time facility: An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that do not require a call to operating system services. The facility includes an instruction that determines elapsed time and reports it to the user as... Agent: International Business Machines Corporation
20130311758 - Hardware profiling mechanism to enable page level automatic binary translation: A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a... Agent:
20130311759 - Instruction sequence buffer to enhance branch prediction efficiency: A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch... Agent: Soft Machines, Inc.
20130311760 - Multi level indirect predictor using confidence counter and program counter address filter scheme: The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program... Agent: Qualcomm Incorporated11/14/2013 > 14 patent applications in 8 patent subcategories.
20130305011 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself... Agent:
20130305012 - Implementation of counters using trace hardware: A multi-core computing system includes a plurality of processor cores, a counter, and a register block including a plurality of event registers coupled to the plurality of processor cores. Each of the plurality of processor cores is configured to write event records to the event registers, and the register block... Agent: Telefonaktiebolaget L M Ericsson (publ)
20130305014 - Microprocessor that enables arm isa program to access 64-bit general purpose registers written by x86 isa program: A microprocessor includes hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. The microprocessor also includes hardware registers that instantiate the ARM Architecture GPRs. In response to an ARM MRRC instruction that specifies the respective... Agent: Via Technologies, Inc.
20130305013 - Microprocessor that makes 64-bit general purpose registers available in msr address space while operating in non-64-bit mode: A microprocessor includes hardware registers that instantiate the IA-32 Architecture EDX and EAX GPRs and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. In response to an IA-32 Architecture RDMSR instruction that specifies the... Agent: Via Technologies, Inc.
20130305015 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself... Agent:
20130305016 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself... Agent:
20130305017 - Compiled control code parallelization by hardware treatment of data dependency: An apparatus comprising a buffer and a processor. The buffer may be configured to store a plurality of fetch sets. The processor may be configured to perform a change of flow operation based upon at least one of (i) a comparison between addresses of two memory locations involved in each... Agent:
20130305019 - Instruction and logic to control transfer in a partial binary translation system: A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The... Agent:
20130305018 - Mfence and lfence micro-architectural implementation method and system: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The... Agent:
20130305020 - Vector friendly instruction format and execution thereof: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier... Agent:
20130305021 - Method for convergence analysis based on thread variance analysis: Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control dependence on a block that is either divergent or comprising a variant branch condition. Convergent basic blocks that are defined by invariant... Agent:
20130305022 - Speeding up younger store instruction execution after a sync instruction: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The... Agent: International Business Machines Corporation
20130305023 - Execution of a perform frame management function instruction: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.... Agent:
20130305024 - Method and system using exceptions for code specialization in a computer architecture that supports transactions: A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied... Agent:Previous industry: Electrical computers and digital processing systems: memory
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