Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions

20090276606 - Method and system for parallel histogram calculation in a simd and vliw processor: The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of histogram calculation by a factor of N times over a scalar processor where the SIMD processor could perform N LUT operations... Agent: Sawyer Law Group PC

20090276607 - Virtualization platform with dedicated cache access: A computing system supports a virtualization platform with dedicated cache access. The computing system is configured for usage with a memory and a cache and comprises an instruction decoder configured to decode a cache-line allocation instruction and control logic. The control logic is coupled to the instruction decoder and controls... Agent: Hewlett-packard Company Intellectual Property Administration

20090276608 - Micro processor, method for encoding bit vector, and method for generating bit vector: In a microprocessor for pipeline processing instruction execution, dependency relationship information representing a dependency relationship of each of a plurality of instructions with all the preceding instructions is stored, and whether or not the instructions in stages after instruction issue depend on the instruction of a miss speculation is judged... Agent: Gerald E. Hespos Casella & Hespos LLP

20090276609 - Configurable pipeline based on error detection mode in a data processing system: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor... Agent: Freescale Semiconductor, Inc. Law Department

20090276610 - Test case generation with backward propagation of predefined results and operand dependencies: A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structure in a forwards manner, and calculating a result for the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090276611 - Ram block branch history table in a global history branch prediction system: Provided is a means for accessing multiple entries from a branch history table (BHT) in a single clock cycle, in the context of pipelined instruction processing. In a first clock cycle, a plurality of conditional branch instructions is fetched. A value is accessed from a global history record (GHR) of... Agent: Gerald W. Maliszewski

20090271591 - Vector simd processor: A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction... Agent: Miles & Stockbridge PC

20090271592 - Apparatus for storing instructions in a multithreading microprocessor: A circuit for selecting one of N requesters in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090271593 - Patching device for patching rom code, method for patching rom code, and electronic device utilizing the same: An electronic device comprising a ROM, a reprogrammable memory, a processor, and a patching device. The ROM stores a first function starting from a first address, the reprogrammable memory stores a second function starting from a second address, the patching device couples to the ROM and the reprogrammable memory, and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090271594 - Semiconductor integrated circuit, semiconductor integrated circuit control device, load distribution method, load distribution program, and electronic device: A damage control unit includes: a switching judgment unit to judge the CPU configuration which performs smoothing of the damage ratio, according to the damage ratio of the CPUs; and a switching unit to perform switching of I/O signals of all the CPUs. The switching judgment unit observes the damage... Agent: Nec Corporation Of America

20090271595 - Configuring an application for execution on a parallel computer: Methods, systems, and products are disclosed for configuring an application for execution on a parallel computer that include: booting up a first subset of a plurality of nodes in a serial processing mode; booting up a second subset of the plurality of nodes in a parallel processing mode; profiling, prior... Agent: Ibm (roc-blf)

20090271596 - Executing an application on a parallel computer: Methods, systems, and products are disclosed for executing an application on a parallel computer having a plurality of nodes. Executing an application on a parallel computer includes: booting up a first subset of a plurality of nodes in a serial processing mode; booting up a second subset of the plurality... Agent: Ibm (roc-blf)

20090271597 - Branch prediction in a computer processor: Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most... Agent: Ibm (roc-blf)

20090265527 - Multiport execution target delay queue fifo array: One embodiment provides a method of forwarding data in a processor. The method generally includes providing at least one cascaded delayed execution pipeline unit having at least a first pipeline and a second pipeline for executing first and second instructions in a common issue group, wherein the second pipeline executes... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090265528 - Programmable streaming processor with mixed precision instruction execution: The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and... Agent: Qualcomm Incorporated

20090265529 - Processor apparatus and method of processing multiple data by single instructions: A processor (and method) of processing multiple data by a single instruction includes first and second register sets each of which includes a plurality of registers, and an arithmetic unit to rearrange data being registered in the first and second register sets according to a relative size of an absolute... Agent: Mcginn Intellectual Property Law Group, PLLC

20090265531 - Code evaluation for in-order processing: Systems and methods of code evaluation for in-order processing are disclosed. In an embodiment, the method includes identifying a first instruction having multiple execution source paths. The method also includes generating a first execution path model identifying an execution order of multiple instructions based on a first condition and generating... Agent: Qualcomm Incorporated

20090265530 - Latency hiding of traces using block coloring: An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information. The blocks correspond to a program trace and containing a wait instruction. The wait instruction is sunk down the... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090265532 - Anti-prefetch instruction: Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090265533 - Branch prediction mechanisms using multiple hash functions: In one embodiment, the branch prediction mechanism includes a first storage including a first plurality of locations for storing a first set of partial prediction information. The branch prediction mechanism also includes a second storage including a second plurality of locations for storing a second set of partial prediction information.... Agent: Mhkkg/sun

20090265534 - Fairness, performance, and livelock assessment using a loop manager with comparative parallel looping: A method, apparatus, and computer program are provided for assessing fairness, performance, and livelock in a logic development process utilizing comparative parallel looping. Multiple loop macros are generated, the multiple loop macros respectively correspond to multiple processor threads, and the multiple loop macros are parallel comparative loop macros. The multiple... Agent: Cantor Colburn LLP - IBM Rochester Division