|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/21/2015 > 17 patent applications in 10 patent subcategories.
20150143073 - Data processing systems: A data processing system is described in which a plurality of data processing units 521 . . . 52N cooperate with one another in order to process incoming data packets or an incoming data stream. Tasks are managed using a task list which is accessible and updateable by each data... Agent: Bluwireless Technology Limited
20150143074 - Vector exception code: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The... Agent:
20150143075 - Vector generate mask instruction: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the... Agent:
20150143080 - Vector checksum instruction: Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out... Agent:
20150143078 - Vector processing engines (vpes) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption are disclosed. Related vector processor systems and methods are also disclosed. The VPEs are configured to provide filter vector processing operations. To minimize re-fetching of input vector data... Agent: Qualcomm Incorporated
20150143076 - Vector processing engines (vpes) employing despreading circuitry in data flow paths between execution units and vector data memory to provide in-flight despreading of spread-spectrum sequences, and related vector processing instructions, systems, and meth: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow... Agent: Qualcomm Incorporated
20150143077 - Vector processing engines (vpes) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory, and related vector processing instructions, sys: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow... Agent: Qualcomm Incorporated
20150143079 - Vector processing engines (vpes) employing tapped-delay line(s) for providing precision correlation / covariance vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision correlation/covariance vector processing operations with reduced sample re-fetching and/or power consumption are disclosed. The VPEs disclosed herein are configured to provide correlation/covariance vector processing operations, such as code division multiple access (CDMA) correlation/covariance vector processing operations as a non-limiting... Agent: Qualcomm Incorporated
20150143081 - Processor capable of supporting multimode and multimode supporting method thereof: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence,... Agent: Samsung Electronics Co., Ltd.
20150143082 - Dynamically erectable computer system: A fault-tolerant computer system architecture includes two types of operating domains: a conventional first domain (DID) that processes data and instructions, and a novel second domain which includes mentor processors for mentoring the DID according to “meta information” which includes but is not limited to data, algorithms and protective rule... Agent:
20150143083 - Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction: Techniques for increasing vector processing utilization and efficiency through use of unmasked lanes of predicated vector instructions for executing non-conflicting instructions are provided. In one aspect, a method of vector lane predication for a processor is provided which includes the steps of: fetching predicated vector instructions from a memory; decoding... Agent: International Business Machines Corporation
20150143084 - Hand held device to perform a bit range isolation instruction: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value... Agent: Intel Corporation
20150143087 - Service system and method: A system includes provision of a first set of instructions associated with a product to a user of the product, the user having one or more associated characteristics, reception of a revision to the first set of instructions from the user, determination of whether to modify the first set of... Agent: General Electric Company
20150143088 - Vector element rotate and insert under mask instruction: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the... Agent:
20150143086 - Vector processing engines (vpes) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations, and r: Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided... Agent: Qualcomm Incorporated
20150143085 - Vector processing engines (vpes) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory, and related vector processor systems and: Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths... Agent: Qualcomm Incorporated
20150143089 - System performance enhancement with smi on multi-core systems: Mechanisms for providing enhanced system performance and reliability on multi-core computing devices are discussed. Embodiments use modified hardware and/or software so that when a System Management Interrupt (SMI#) is generated, only a single targeted CPU core enters System Management Mode (SMM) in response to the SMI while the remaining CPU... Agent:05/14/2015 > 9 patent applications in 8 patent subcategories.
20150134931 - Method and apparatus to represent a processor context with fewer bits: According to at least one example embodiment, a method and corresponding processor device comprise maintaining a translation data structure mapping uncompressed process context identifiers to corresponding compressed identifiers, the uncompressed process context identifiers and the corresponding compressed identifiers being associated with address spaces or corresponding computer processes. The compressed identifiers... Agent: Cavium, Inc.
20150134932 - Structure access processors, methods, systems, and instructions: A method of an aspect, which may be performed responsive to one or more structure access instructions, includes changing a state of a portion of a structure of a processor to a sequestered state. In the sequestered state, components of the processor are not able to access the portion of... Agent:
20150134933 - Adaptive prefetching in a data processing apparatus: A data processing apparatus and method of data processing are disclosed. An instruction execution unit executes a sequence of program instructions, wherein execution of at least some of the program instructions initiates memory access requests to retrieve data values from a memory. A prefetch unit prefetches data values from the... Agent: Arm Limited
20150134934 - Virtual load store queue having a dynamic dispatch window with a distributed structure: An out of order processor. The processor includes a distributed load queue and a distributed store queue that maintain single program sequential semantics while allowing an out of order dispatch of loads and stores across a plurality of cores and memory fragments; wherein the processor allocates other instructions besides loads... Agent:
20150134935 - Split register file for operands of different sizes: In an embodiment, a processor includes a register file having multiple widths corresponding to different operands sizes of a given data type implemented by the processor. For example, the integer register file may have 32 bit and 64 bit widths for 32 and 64 bit operand sizes. The register file... Agent: Apple Inc.
20150134936 - Single instruction multiple data add processors, methods, systems, and instructions: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device... Agent:
20150134938 - Image processing device, instruction processing method, and computer program product: An image processing device includes an operation unit and is able to receive a plurality of operation instructions in parallel from the operation unit and a portable information processing terminal. The image processing device includes: an instruction processing unit that executes processing according to the received operation instructions. The instruction... Agent:
20150134937 - Simd variable shift and rotate using control manipulation: Vector single instruction multiple data (SIMD) shift and rotate instructions are provided specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, and a second vector register. Vector data fields of a first element size are duplicated. Duplicate vector data fields... Agent: Intel Corporation
20150134939 - Information processing system, information processing method and memory system: An information processing system is provided. The information processing system includes a processor used to obtain information, a memory used to store the information and output an information block based on a received address; and a scanner used to generate an address based on the current information block and to... Agent:05/07/2015 > 6 patent applications in 6 patent subcategories.
20150127924 - Method and apparatus for processing shuffle instruction: A method and corresponding apparatus for processing a shuffle instruction are provided. Shuffle units are configured in a hierarchical structure, and each of the shuffle units generates a shuffled data element array by performing shuffling on an input data element array. In the hierarchical structure, which includes an upper shuffle... Agent: Samsung Electronics Co., Ltd.
20150127925 - Computing architecture for operating on sequential data: A data stream processing unit (DPU) and method for use are provided. A DPU includes a number of processing elements arranged in a sequence, and each datum in the data stream visits each processing element in sequence. Each processing element has a memory circuit, data and metadata input and output... Agent:
20150127926 - Instruction scheduling approach to improve processor performance: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at... Agent:
20150127927 - Efficient hardware dispatching of concurrent functions in multicore processors, and related processor systems, methods, and computer-readable media: Embodiments of the disclosure provide efficient hardware dispatching of concurrent functions in multicore processors, and related processor systems, methods, and computer-readable media. In one embodiment, a first instruction indicating an operation requesting a concurrent transfer of program control is detected in a first hardware thread of a multicore processor. A... Agent: Qualcomm Incorporated
20150127928 - Energy efficient multi-modal instruction issue: A processor is described herein that is configured to switch between a first instruction issue mode of the processor and a second instruction issue mode of the processor based at least in part on a characteristic associated with a plurality of instructions. The first instruction issue mode and the second... Agent: Microsoft Corporation
20150127929 - Data processing device and method of controlling the same: A data processing device includes an instruction executing part executing a normal task and a management task scheduling an execution order of the normal task with switching the normal task and the management task, a counter measuring an execution state of the normal task being executed in the instruction executing... Agent:04/30/2015 > 16 patent applications in 12 patent subcategories.
20150121036 - Cryptographic support instructions: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction... Agent:
20150121037 - Computing architecture and method for processing data: A processing device includes an execute processor configured to execute data processing instructions; and an access processor configured to be coupled with a memory system to execute memory access instructions; wherein the execute processor and the access processor are logically separated units, the execute processor having an execute processor input... Agent:
20150121039 - Method and apparatus for shuffling data: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the... Agent: Intel Corporation
20150121038 - Prefetch strategy control: A single instruction multiple thread (SIMT) processor 2 includes execution circuitry 6, prefetch circuitry 12 and prefetch strategy selection circuitry 14. The prefetch strategy selection circuitry serves to detect one or more characteristics of a stream of program instructions that are being executed to identify whether or not a given... Agent: Arm Limited
20150121040 - Processor and methods for floating point register aliasing: Methods, devices, and systems for accessing packed registers are presented. A state of the packed registers may be tracked and it may be determined whether the register is directly accessible based on the state. If the register is not directly accessible, an action may be performed which allows the register... Agent: Advanced Micro Devices, Inc.
20150121041 - Processor and methods for immediate handling and flag handling: Described herein are methods and processors for flag renaming in groups to eliminate dependencies of instructions. Decoder and execution units in the processor may be configured to rename flags into groups that allow each group to be treated separately as appropriate. This flag renaming eliminates flag dependencies with respect to... Agent: Advanced Micro Devices, Inc.
20150121042 - Arithmetic device: According to an embodiment, an arithmetic device includes an arithmetic processing unit, an address generating unit, and a control unit. The arithmetic processing unit performs a plurality of arithmetic processing used in an encryption method. Based on an upper bit of the address of the first piece of data and... Agent: Kabushiki Kaisha Toshiba
20150121043 - Computer and methods for solving math functions: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for... Agent: Texas Instruments Incorporated
20150121044 - Merged floating point operation using a modebit: A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a... Agent:
20150121046 - Ordering and bandwidth improvements for load and store unit and data cache: The present invention provides a method and apparatus for supporting embodiments of an out-of-order load to load queue structure. One embodiment of the apparatus includes a load queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes a load order... Agent: Advanced Micro Devices, Inc.
20150121045 - Reading a register pair by writing a wide register: A read operation is initiated to obtain a wide input operand. Based on the initiating, a determination is made as to whether the wide input operand is available in a wide register or in two narrow registers. Based on determining the wide input operand is not available in the wide... Agent: International Business Machines Corporation
20150121047 - Reading a register pair by writing a wide register: A read operation is initiated to obtain a wide input operand. Based on the initiating, a determination is made as to whether the wide input operand is available in a wide register or in two narrow registers. Based on determining the wide input operand is not available in the wide... Agent:
20150121048 - Heterogeneity within a processor core: A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends... Agent: The Regents Of The University Of Michigan
20150121049 - Safe conditional-load and conditional-store operations: One embodiment is a computer-implemented method for safe conditional operation when storage access cannot be proven safe. The method includes receiving a portion of source code for a transaction by an enhanced compiler and. The portion of source code received is analyzed, by the enhanced compiler, to determine whether the... Agent:
20150121050 - Bandwidth increase in branch prediction unit and level 1 instruction cache: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP).... Agent: Advanced Micro Devices, Inc.
20150121051 - Kernel functionality checker: A debugging system and method, referred to as a kernel functionality checker, is described for enabling debugging of software written for device-specific APIs (application program interfaces) without requiring support or changes in the software driver or hardware. Specific example embodiments are described for OpenCL, but the disclosed methods may also... Agent:Previous industry: Electrical computers and digital processing systems: memory
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