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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

20130117533 - Coprocessor having task sequence control: A coprocessor has: a processing unit for processing tasks in a data-processing system subject to at least one master processor; at least one storage module having memory areas, assignable in each case to the tasks, for storing data assigned to the tasks; and a buffer area for buffering instructions assigned... Agent:

20130117534 - Instruction and logic for processing text strings: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding... Agent:

20130117536 - Reconfigurable instruction encoding method and processor architecture: A reconfigurable instruction encoding method includes the followings. An instruction distribution of an application is counted, and multiple instruction pairs with higher utilization rates are accordingly found. Multiple instructions of the instruction pairs are duplicately encoded according to multiple reserved sections of an original instruction table, so that the instructions... Agent: Industrial Technology Research Institute

20130117535 - Selective writing of branch target buffer: A method includes executing a branch instruction and determining if a branch is taken. The method further includes evaluating a number of instructions associated with the branch instruction. Upon determining that the branch is taken, the method includes selectively writing an entry into a branch target buffer that corresponds to... Agent: Qualcomm Incorporated

20130117537 - Method and apparatus for unpacking packed data: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed... Agent:

20130117538 - Method and apparatus for unpacking packed data: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed... Agent:

20130117539 - Method and apparatus for packing packed data: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed... Agent:

20130117540 - Method and apparatus for unpacking packed data: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed... Agent:

20130117541 - Speculative execution and rollback: One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of other instructions. A scheduler circuit issues instructions for execution assuming that, several cycles later, when the instructions reach multithreaded execution units, that... Agent:

20130117542 - Code coverage framework: A method, information processing system, and computer program product record an execution of a program instruction. A determination is made that a thread has entered a program unit. Another determination is made that that the thread is associated with at least one attribute that matches a set of thread recording... Agent: International Business Machines Corporation

20130117545 - High-word facility for extending the number of general purpose registers available to instructions: A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a... Agent: International Business Machines Corporation

20130117543 - Low overhead operation latency aware scheduler: A method and apparatus for processing multi-cycle instructions include picking a multi-cycle instruction and directing the picked multi-cycle instruction to a pipeline. The pipeline includes a pipeline control configured to detect a latency and a repeat rate of the picked multi-cycle instruction and to count clock cycles based on the... Agent: Advanced Micro Devices, Inc.

20130117544 - Method and apparatus for run-time statistics dependent program execution using source-coding principles: Disclosed are a method and system for optimized, dynamic data-dependent program execution. The disclosed system comprises a statistics computer which computes statistics of the incoming data at the current time instant, where the said statistics include the probability distribution of the incoming data, the probability distribution over program modules induced... Agent: International Business Machines Corporation

20130117546 - Load pair disjoint facility and instruction therefore: A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs.... Agent: International Business Machines Corporation

20130117547 - Method and apparatus for unpacking and moving packed data: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed... Agent:

20130117548 - Algorithm for vectorization and memory coalescing during compiling: One embodiment of the present invention sets forth a technique for reducing the number of assembly instructions included in a computer program. The technique involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, where each node includes an assembly instruction of the computer program, hierarchically parsing... Agent: Nvidia Corporation

20130111188 - Low latency massive parallel data processing device: Data processing device comprising a multidimensional array of ALUs, having at least two dimension where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array.... Agent:

20130111189 - Circuit arrangement for a data processing system and method for data processing: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement... Agent: Robert Bosch Gmbh

20130111190 - Operational code expansion in response to successive target address detection: A circuit arrangement and method support compression and expansion of instruction opcodes by detecting successive address targeting and decoding a first opcode of an instruction into a second opcode in response to detecting successive address targeting. The circuit arrangement and method execute instructions in an instruction stream and detect successive... Agent: International Business Machines Corporation

20130111191 - Processor instruction issue throttling: A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The... Agent:

20130111192 - Adjusting acknowledgement requests for remote control transmissions based on previous acknowledgements: A remote receives an instruction to transmit and determines whether or not to include an acknowledgement request in the instruction based on statistics regarding receipt of acknowledgements associated with previously transmitted instructions. If so, the remote control device includes the request before transmitting. The remote control may determine whether or... Agent: Echostar Technologies L.L.C.

20130111193 - Running shift for divide instructions for processing vectors: In the described embodiments, a processor generates a result vector when executing a RunningShiftForDivide1P or RunningShiftForDivide2P instruction. In these embodiments, upon executing a RunningShiftForDivide1P/2P instruction, the processor receives a first input vector and a second input vector. The processor then records a base value from an element at a key... Agent: Apple Inc.

20130111194 - Method and system to provide user-level multithreading: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or... Agent:

20130111195 - Data processing system with safe call and return: Embodiments of a system and method are disclosed that can include a memory unit, and a memory management unit coupled to the memory unit. The memory management unit can include address mapping circuitry and access control circuitry operable to: provide address mappings for at least a frame stack and a... Agent:

20130103925 - Method and system for folding a simd array: Systems and methods for folding a single instruction multiple data (SIMD) array include a newly defined processing element group (PEG) that allows interconnection of PEGs by abutment without requiring a row or column weave pattern. The interconnected PEGs form a SIMD array that is effectively folded at its center along... Agent: Geo Semiconductor, Inc.

20130103926 - Establishing a data communications connection between a lightweight kernel in a compute node of a parallel computer and an input-output ('i/o') node of the parallel computer: Establishing a data communications connection between a lightweight kernel in a compute node of a parallel computer and an input-output (‘I/O’) node of the parallel computer, including: configuring the compute node with the network address and port value for data communications with the I/O node; establishing a queue pair on... Agent: International Business Machines Corporation

20130103927 - Characterization and validation of processor links: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One... Agent: International Business Machines Corporation

20130103928 - Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal... Agent:

20130103929 - Coupling processors to each other for high performance computing (hpc): A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.... Agent: Raytheon Company

20130103930 - Data processing device and method, and processor unit of same: A processor unit (200) includes: cache memory (210); an instruction execution unit (220); a processing unit (230) that detects fact that a thread enters an exclusive control section which is specified in advance to become a bottleneck; a processing unit (240) that detects a fact that the thread exits the... Agent: Nec Corporation

20130103931 - Machine processor: Disclosed are machine processors and methods performed thereby. The processor has access to processing units for performing data processing and to libraries. Functions in the libraries are implementable to perform parallel processing and graphics processing. The processor may be configured to acquire (e.g., to download from a web server) a... Agent: Motorola Mobility LLC

20130103932 - Multi-addressable register files and format conversions associated therewith: A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be translated from one format to another format. If so determined, a convert machine instruction is executed that obtains a single precision... Agent: International Business Machines Corporation

20130097406 - Cluster computing using special purpose microprocessors: In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node... Agent:

20130097407 - Unified, workload-optimized, adaptive ras for hybrid systems: A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes managing workloads on a first processor with a first processor architecture by an agent process executing on a second processor with a second processor architecture. The method proceeds by... Agent: International Business Machines Corporation

20130097408 - Conditional compare instruction: An instruction decoder (14) is responsive to a conditional compare instruction to generate control signals for controlling processing circuitry (4) to perform a conditional compare operation. The conditional compare operation comprises: (i) if a current condition state of the processing circuitry (4) passes a test condition, then performing a compare... Agent: Arm Limited

20130097409 - Instruction-issuance controlling device and instruction-issuance controlling method: In a multithread processor capable of executing a plurality of threads, in order to select a thread and instruction for increasing a throughput of the multithread processor, an instruction-issuance controlling device included in the multithread processor includes a resource management unit configured to manage stall information indicating whether or not... Agent: Panasonic Corporation

20130097410 - Machine processor: Disclosed are machine processors and methods performed thereby. The processor has access to processing units for performing data processing and to libraries. Functions in the libraries are implementable to perform parallel processing and graphics processing. The processor may be configured to acquire (e.g., to download from a web server) a... Agent: Motorola Mobility LLC

20130097411 - Transferring architected state between cores: A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first... Agent: International Business Machines Corporation