|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/13/2014 > 6 patent applications in 5 patent subcategories.
20140337601 - Configurable logic integrated circuit having a multidimensional structure of configurable elements: An array processor composed of processor cells that are programmed by a controlling unit, and that are reprogrammed when a cell has finished a current data processing operation, even while other cell continue to process data with their current programming.... Agent: Pact Xpp Technologies Ag
20140337602 - Execution of an instruction for performing a configuration virtual topology change: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the... Agent: International Business Machines Corporation
20140337603 - Semiconductor device: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor... Agent:
20140337604 - Minimizing bandwidth to track return targets by an instruction tracing system: A processing device implementing minimizing bandwidth to track return targets by an instruction tracing system is disclosed. A processing device of the disclosure an instruction fetch unit comprising a return stack buffer (RSB) to predict a target address of a return (RET) instruction corresponding to a call (CALL) instruction. The... Agent:
20140337605 - Mechanism for reducing cache power consumption using cache way prediction: A mechanism for reducing power consumption of a cache memory of a processor includes a processor with a cache memory that stores instruction information for one or more instruction fetch groups fetched from a system memory. The cache memory may include a number of ways that are each independently controllable.... Agent: Apple Inc.
20140337606 - Digital signal processor, program control method, and control program: When the branch condition of a branch command for a loop process is satisfied and enters the loop mode, the relative branch address is saved in a branch relative address save circuit that points to the branch command for loop processing, and the loop state flag is set in a... Agent: Nec Corporation11/06/2014 > 8 patent applications in 8 patent subcategories.
20140331025 - Reconfigurable processor and operation method thereof: A reconfigurable processor and an operation method thereof are provided. The reconfigurable processor may include: a controller configured to control operations of a first mode, in which a first portion of a program that does not utilize loop acceleration is processed, and a second mode, in which a second portion... Agent: Samsung Electronics Co., Ltd.
20140331026 - Multi-frame data processing apparatus and method using frame disassembly: A multi-frame data processing apparatus and method using frame disassembly is provided. The multi-frame data apparatus includes a data communication unit, a frame processing unit, and a data processing unit The data communication unit receives a transmission signal from a Line Adaptation Unit (LAU). The frame processing unit disassembles each... Agent: Electronics And Telecommunications Research Institute
20140331027 - Asymmetric mesh noc topologies: A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required... Agent:
20140331028 - Identification of missing call and return instructions for management of a return address stack: A data processing apparatus and method of data processing are disclosed. A fetch unit retrieves program instructions comprising call instructions and return instructions from memory to be executed by an execution unit. A branch prediction unit generates a return address prediction for an identified return instruction with reference to a... Agent: Arm Limited
20140331029 - Synchronisation of execution threads on a multi-threaded processor: Method and apparatus are provided for synchronising execution of a plurality of threads on a multi-threaded processor. A program executed by a thread can have a number of synchronisation points corresponding to points where execution is to be synchronised with another thread. Execution of a thread is paused when it... Agent: Imagination Technologies Limited
20140331030 - Statically speculative compilation and execution: A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the speculative static information in an instruction set architecture of a processor, and executing a compiled computer program using the speculative static information, wherein executing supports... Agent: Bluerisc Inc.
20140331031 - Reconfigurable processor having constant storage register: A reconfigurable processor configured to include a constant storage register to store a constant is provided, thereby improving efficiency in the use of a memory space. Specifically, a reconfigurable processor includes a plurality of Functional Units (FUs), a configuration memory configured to store configuration information, and a constant storage register... Agent: Samsung Electronics Co., Ltd.
20140331032 - Streaming memory transpose operations: According to one general aspect, an apparatus may include a load/store unit, an execution unit, and a first and a second data path. The load/store unit may be configured to load/store data from/to a memory and transmit the data to/from an execution unit, wherein the data includes a plurality of... Agent:10/30/2014 > 14 patent applications in 10 patent subcategories.
20140325180 - Electronic system, central processing unit expansion apparatus, portable electronic apparatus and processing method: An electronic system includes a central processing unit (CPU) expansion apparatus and a portable electronic apparatus. The CPU expansion apparatus has a first CPU connector and a first CPU. The portable electronic apparatus has a second CPU connector and a second CPU. When the first CPU connector is connected to... Agent: National Cheng Kung University
20140325181 - Hierarchical reconfigurable computer architecture: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting... Agent: Stmicroelectronics S.a.
20140325183 - Integrated circuit device, asymmetric multi-core processing module, electronic device and method of managing execution of computer program code therefor: An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is... Agent: Freescale Semiconductor, Inc.
20140325182 - System and method for creating highly scalable high availability cluster in a massively parallel processing cluster of machines in a network: System and method embodiments are provided to implement highly scalable and high availability (HA) clusters in massively parallel processing (MPP) systems. The embodiments include a method to build a highly scalable MPP HA cluster, which provides HA to the cluster while allowing it to scale to relatively larger number of... Agent: Futurewei Technologies, Inc.
20140325184 - Mechanism for saving and retrieving micro-architecture context: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a... Agent:
20140325185 - Method for operating a processor: A method for operating a processor in which a first program comprising a first sequence of commands is provided, at least one second program is provided comprising a second sequence of commands, where the first program comprises a time-critical section with time-critical commands, commands from the first and second programs... Agent: Siemens Aktiengesellschaff
20140325186 - Supporting code execution in dual address spaces: A processing apparatus supports execution of executable computer program code, wherein non-instruction data is read from and written to a first address space, while executable instructions are fetched from a second address space. Preferably, the processing apparatus supports execution of a modified or enhanced computer program. The programs and user... Agent:
20140325187 - Single-cycle instruction pipeline scheduling: A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle... Agent: Advanced Micro Devices, Inc.
20140325188 - Simultaneous finish of stores and dependent loads: A method for reducing a pipeline stall in a multi-pipelined processor includes finding a store instruction having a same target address as a load instruction and having a store value of the store instruction not yet written according to the store instruction, when the store instruction is being concurrently processed... Agent: International Business Machines Corporation
20140325189 - Query sampling information instruction: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data... Agent:
20140325190 - Method for improving execution performance of multiply-add instruction during compiling: The present invention relates to a method for improving execution performance of multiply-add instructions during compiling, comprising the following steps of: compiling a source code by a compiler to acquire internal representation; optimizing; generating a machine code on the basis of a target processor, and allocating a physical register to... Agent: Shenzhen Zhongweidian Technology Limited
20140325191 - Semiconductor test apparatus for controlling tester: A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either... Agent: Renesas Electronics Corporation
20140325193 - Dynamic instrumentation: Techniques for dynamic instrumentation are provided. A method for instrumentation preparation may include obtaining address data of an original instruction in an original instruction stream, obtaining kernel mode data comprising a kernel breakpoint handler, obtaining user mode data comprising a user breakpoint handler, allocating a page of a process address... Agent:
20140325192 - Memristor based multithreading: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first... Agent: Technion Research And Development Foundation Ltd.10/23/2014 > 15 patent applications in 13 patent subcategories.
20140317376 - Digital processor having instruction set with complex angle function: A digital processor, such as a vector processor or a scalar processor, is provided having an instruction set with a complex angle function. A complex angle is evaluated for an input value, x, by obtaining one or more complex angle software instructions having the input value, x, as an input;... Agent: Lsi Corporation
20140317377 - Vector frequency compress instruction: A processor core that includes a hardware decode unit to decode a vector frequency compress instruction that includes a source operand and a destination operand. The source operand specifying a source vector register that includes a plurality of source data elements including one or more runs of identical data elements... Agent:
20140317378 - Scheduling in a multicore architecture: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling... Agent: Fujitsu Semiconductor Limited
20140317379 - Information processing system, control apparatus, and method of controlling information processing system: A parallel computer includes a plurality of processors connected through transmission paths to each other. A job management server determines a communication path passing transmission paths connecting a certain number of processors in accordance with jobs to be input among the processors, and inputs the jobs to the certain number... Agent: Fujitsu Limited
20140317380 - Multi-core processor: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core.... Agent: Denso Corporation
20140317381 - Method of processing immediate value in eisc processor: Disclosed is a method of operating an immediate value in an extendable instruction set computer (EISC) processor, comprising: checking whether or not an unsigned immediate value is used to generate an extension register (ER) value for operating an immediate value; and generating the ER value by performing zero extension for... Agent: Advanced Digital Chips Inc.
20140317382 - Dynamic configuration of processing pipeline based on determined type of fetched instruction: Various embodiments relating to executing different types of instruction code in a micro-processing system are provided. In one embodiment, a micro-processing system includes a memory/storage subsystem configured to store non-native instruction set architecture (ISA) code and native ISA code in a common address space, fetch logic configured to retrieve the... Agent: Nvidia Corporation
20140317383 - Apparatus and method for compressing instruction for vliw processor, and apparatus and method for fetching instruction: Provided are an instruction compression apparatus and method for a very long instruction word (VLIW) processor, and an instruction fetching apparatus and method. The instruction compression apparatus includes: an indicator generator configured to generate an indicator code that indicates an issue width of an instruction bundle to be executed in... Agent: Samsung Electronics Co., Ltd.
20140317384 - Data processing apparatus and method for pre-decoding instructions to be executed by processing circuitry: A hierarchical cache with at least a unified cache is used to store both instructions and data values, and a further cache coupled between processing circuitry and a unified cache. The unified cache has a plurality of cache lines identified as an instruction cache line or a data cache line.... Agent: Arm Limited
20140317385 - Techniques for determining instruction dependencies: One embodiment sets forth a method for efficiently determining memory resource dependencies between instructions included in a software application. For each instruction, a dependency analyzer uses overlapping search techniques to identify one or more overlaps between the memory elements included in the current instruction and the memory elements included in... Agent: Nvidia Corporation
20140317386 - Techniques for determining instruction dependencies: One embodiment sets forth a method for efficiently determining memory resource dependencies between instructions included in a software application. For each instruction, a dependency analyzer uses overlapping search techniques to identify one or more overlaps between the memory elements included in the current instruction and the memory elements included in... Agent: Nvidia Corporation
20140317387 - Method for performing dual dispatch of blocks and half blocks: A method for executing dual dispatch of blocks and half blocks. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute... Agent: Soft Machines, Inc.
20140317388 - Apparatus and method for supporting multi-modes of processor: An apparatus and method for supporting a multi-mode. The apparatus for supporting a multi-mode may include an instruction distributor configured to select, according to a current execution mode, at least one instruction from among a plurality of received instructions that each include an operand and an opcode, and transfer the... Agent: Samsung Electronics Co., Ltd.
20140317389 - Computational sprinting using multiple cores: A multi-core processing system that uses computational sprinting to generate high levels of computational output for short periods of time at power consumption levels that are not sustainable over longer periods of time due to thermal and/or other constraints. This is done using a number of processing cores that, when... Agent: The Trustees Of The University Of Pennsylvania
20140317390 - Return address prediction: A data processing apparatus executes call instructions, and after a sequence of instructions executed in response to a call instruction a return instruction causes the program flow to return to a point in the program sequence associated with that call instruction. The data processing apparatus is configured to speculatively execute... Agent: Arm LimitedPrevious industry: Electrical computers and digital processing systems: memory
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