|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/05/2015 > 20 patent applications in 16 patent subcategories.
20150039852 - Data compaction using vectorized instructions: Techniques for performing database operations using vectorized instructions are provided. In one technique, data compaction is performed using vectorized instructions to identify a shuffle mask based on matching bits and update an output array based on the shuffle mask and an input array. In a related technique, a hash table... Agent: Oracle International Corporation
20150039853 - Estimating a cost of performing database operations using vectorized instructions: Techniques for performing database operations using vectorized instructions are provided. In one technique, it is determined whether to perform a database operation using one or more vectorized instructions or without using any vectorized instructions. This determination may comprise estimating a first cost of performing the database operation using one or... Agent: Oracle International Corporation
20150039851 - Methods, apparatus, instructions and logic to provide vector sub-byte decompression functionality: Methods, apparatus, instructions and logic provide SIMD vector sub-byte decompression functionality. Embodiments include shuffling a first and second byte into the least significant portion of a first vector element, and a third and fourth byte into the most significant portion. Processing continues shuffling a fifth and sixth byte into the... Agent:
20150039854 - Vectorized lookup of floating point values: Systems and techniques disclosed herein include methods for de-quantization of feature vectors used in automatic speech recognition. A SIMD vector processor is used in one embodiment for efficient vectorized lookup of floating point values in conjunction with fMPE processing for increasing the discriminative power of input signals. These techniques exploit... Agent: Nuance Communications, Inc.
20150039855 - Methods and apparatus for signal flow graph pipelining that reduce storage of temporary variables: A system for pipelining signal flow graphs by a plurality of shared memory processors organized in a 3D physical arrangement with the memory overlaid on the processor nodes that reduces storage of temporary variables. A group function formed by two or more instructions to specify two or more parts of... Agent:
20150039856 - Efficient complex multiplication and fast fourier transform (fft) implementation on the manarray architecture: Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations... Agent: Altera Corporation
20150039857 - Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC... Agent:
20150039858 - Reducing register read ports for register pairs: Embodiments relate to reducing a number of read ports for register pairs. An aspect includes executing an instruction. The instruction identifies a pair of registers as containing a wide operand which spans the pair of registers. It is determined if a pairing indicator associated with the pair of registers has... Agent:
20150039859 - Microprocessor accelerated code optimizer: A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a... Agent:
20150039860 - Rda checkpoint optimization: A system and method for efficiently performing microarchitectural checkpointing. A register rename unit within a processor determines whether a physical register number qualifies to have duplicate mappings. Information for maintenance of the duplicate mappings is stored in a register duplicate array (RDA). To reduce the penalty for misspeculation or exception... Agent: Apple Inc.
20150039861 - Allocation of alias registers in a pipelined schedule: In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes... Agent:
20150039862 - Techniques for increasing instruction issue rate and reducing latency in an out-of-order processor: A technique for operating a processor includes storing a first result to a writeback buffer, in response to a first execution unit of the processor attempting to write the first result of a first completed instruction to a register file of the processor at a same processor time as a... Agent: International Business Machines Corporation
20150039864 - Systems and methods for defeating malware with randomized opcode values: A computer processor includes a first instruction set and a second instruction set. The computer processor further includes a translator. The translator translates the first instruction set into the second instruction set. The computer processor is configured to execute operations using only the second complete instruction set.... Agent: Ebay Inc.
20150039865 - Control device for vehicle: In a control device for vehicle according to the invention, a data buffer is multiplexed and each arithmetic unit carries out update processing and reference processing to a different multiplexed data buffer. Also, an arithmetic unit that is different from the arithmetic unit executing the data update processing synchronizes one... Agent:
20150039866 - Computer for amdahl-compliant algorithms like matrix inversion: A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the instructed resources is local, dispensing with the need for large VLIW memories. The cores through the PES have maximum performance for Amdahl-compliant... Agent: Qsigma, Inc.
20150039867 - Instruction source specification: Techniques are disclosed relating to specification of instruction operands. In some embodiments, this may involve assigning operands to source inputs. In one embodiment, an instruction includes one or more mapping values, each of which corresponds to a source of the instruction and each of which specifies a location value. In... Agent: Apple Inc.
20150039868 - Intra-instructional transaction abort handling: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation... Agent:
20150039869 - Handling operating system (os) transitions in an unbounded transactional memory (utm) mode: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the... Agent:
20150039870 - Systems and methods for locking branch target buffer entries: A data processing system includes a processor configured to execute processor instructions and a branch target buffer having a plurality of entries. Each entry is configured to store a branch target address and a lock indicator, wherein the lock indicator indicates whether the entry is a candidate for replacement, and... Agent:01/29/2015 > 12 patent applications in 10 patent subcategories.
20150032990 - Scalable and parameterized vlsi architecture for compressive sensing sparse approximation: Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process... Agent: The Regents Of The University Of California
20150032992 - Data processing arrangement and method for data processing: A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that... Agent:
20150032991 - Systems and methods for increasing the energy scale of a quantum processor: Increasing the energy scale of a quantum processor improves its performance. Energy scale of a quantum processor may be increased by increasing the coupling strength of communicatively coupled superconducting devices comprised in the quantum processor. Configuring the physical dimensions of communicatively coupled superconducting devices such that an intentional direct coupling... Agent:
20150032993 - Systems and methods for achieving orthogonal control of non-orthogonal qubit parameters: Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter... Agent:
20150032994 - Systems and methods for improving the performance of a quantum processor by reducing errors: Techniques for improving the performance of a quantum processor are described. Some techniques employ improving the processor topology through design and fabrication, reducing intrinsic/control errors, reducing thermally-assisted errors and methods of encoding problems in the quantum processor for error correction.... Agent:
20150032995 - Processors operable to allow flexible instruction alignment: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported... Agent: Altera Corporation
20150032996 - Execution-aware memory protection: Execution-Aware Memory protection technologies are described. A processor includes an instruction fetch unit to fetch instructions of applications executing in a multitasking environment and an execution unit to execute the instructions. A memory protection unit (MPU) enforces memory access control of the applications by defining an instruction region (I-space) and... Agent:
20150032997 - Tracking long ghv in high performance out-of-order superscalar processors: Tracking global history vector in high performance out of order superscalar processors, in one aspect, may comprise providing a shift register storing global history vector that stores branch predictions and outcomes. A counter is maintained to determine a number of bits to shift the shift register to recover branch history.... Agent: International Business Machines Corporation
20150032998 - Method, apparatus, and system for transactional speculation control instructions: An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision... Agent:
20150032999 - Instruction set architecture with opcode lookup using memory attribute: A method and circuit arrangement decode instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection... Agent: International Business Machines Corporation
20150033000 - Parallel processing array of arithmetic unit having a barrier instruction: A parallel processing array processor has a plurality of arithmetic units and a unit that manages barrier instructions whereby processing of program sequences may be coordinated. The array processor further comprises a hierarchy of assigned units whereby multiple program sequences may be processed in parallel.... Agent: Pact Xpp Technologies Ag
20150033001 - Method, device and system for control signalling in a data path module of a data stream processing engine: Techniques and mechanisms for exchanging control signals in a data path module of a data stream processing engine. In an embodiment, the data path module may be configured to form a set of one or more data paths corresponding to an instruction which is to be executed. In another embodiment,... Agent:01/22/2015 > 14 patent applications in 10 patent subcategories.
20150026433 - Allocation method, apparatus, and program for architectural register: An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register... Agent:
20150026432 - Dynamic formation of symmetric multi-processor (smp) domains: Symmetric multi-processor (SMP) nodes are dynamically configured via SMP sockets that use SMP optically-connected switches to dynamically connect SMP optically-connected links connected to the SMP nodes to form SMP domains based on best matched expected workloads for coherent traffic for exchanging SMP coherent information. The SMP nodes are dynamically added... Agent:
20150026434 - Configurable logic constructs in a loop buffer: Techniques are described herein for using configurable logic constructs in a loop buffer. In an embodiment, a configurable hardware block is programmed based on one or more target functions within a loop. The configurable hardware block is associated with a plurality of registers, including a loopcount register and a first... Agent: Oracle International Corporation
20150026435 - Instruction set architecture with extensible register addressing: A method and circuit arrangement selectively source and/or write data from/to extended registers of an extended register file based in part on whether an operand address of an instruction references a primary register of primary register file configured to store a pointer to the extended register. Control logic connected to... Agent: International Business Machines Corporation
20150026436 - Hybrid tag scheduler: The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry... Agent: Advanced Micro Devices, Inc.
20150026437 - Method and apparatus for differential checkpointing: A processor core stores information that maps a physical register to an architectural register in response to an instruction modifying the architectural register. The processor recovers a checkpointed state of a set of architectural registers prior to modification of the architectural register by the instruction by modifying a reference mapping... Agent:
20150026438 - System, method, and computer program product for cooperative multi-threading for vector threads: A system, method, and computer program product for ensuring forward progress of threads that implement divergent operations in a single-instruction, multiple data (SIMD) architecture is disclosed. The method includes the steps of allocating a queue data structure to a thread block including a plurality of threads, determining that a current... Agent:
20150026440 - Apparatus and method for performing a permute operation: An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for... Agent:
20150026439 - Apparatus and method for performing permute operations: An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for... Agent:
20150026441 - Method and system of inserting marking values used to correlate trace data as between processor cores: A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising... Agent: Texas Instruments Incorporated
20150026442 - System, method, and computer program product for managing out-of-order execution of program instructions: A method, system and computer program product embodied on a computer-readable medium are provided for managing the execution of out-of-order instructions. The method includes the steps of receiving a plurality of instructions and identifying a subset of instructions in the plurality of instructions to be executed out-of-order.... Agent: Nvidia Corporation
20150026443 - Branching to alternate code based on runahead determination: The description covers a system and method for operating a micro-processing system having a runahead mode of operation. In one implementation, the method includes providing, for a first portion of code, a runahead correlate. When the first portion of code is encountered by the micro-processing system, a determination is made... Agent:
20150026444 - Compiler-control method for load speculation in a statically scheduled microprocessor: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load... Agent:
20150026445 - Processor testing: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second... Agent:01/15/2015 > 15 patent applications in 12 patent subcategories.
20150019835 - Predication methods for vector processors: A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.... Agent:
20150019836 - Register file structures combining vector and scalar data with global and local accesses: The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths... Agent:
20150019837 - Data processor: A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers... Agent:
20150019838 - Vector load and duplicate operations: A method of loading and duplicating scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.... Agent:
20150019839 - Determining processor offsets to synchronize processor time values: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A... Agent:
20150019840 - Highly integrated scalable, flexible dsp megamodule architecture: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to... Agent:
20150019841 - Anticipated prefetching for a parent core in a multi-core chip: Embodiments relate to prefetching data on a chip having a scout core and a parent core coupled to the scout core. A method includes determining that a program executed by the parent core requires content stored in a location remote from the parent core. The method includes sending a fetch... Agent:
20150019842 - Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in dsss cellular systems: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real... Agent:
20150019843 - Method and apparatus for selective renaming in a microprocessor: A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed... Agent: Qualcomm Incorporated
20150019845 - Method to extend the number of constant bits embedded in an instruction set: The invention allows a processor to maintain a fixed instruction width regardless of the width of the constants needed. The constant extension solves the problem of having variable length opcodes to accommodate longer constants. The invention allows the architecture to have a fixed width, regardless of the width of the... Agent:
20150019844 - Synthetic processing diversity within a homogeneous processing environment: A method of increasing processing diversity on a computer system includes: loading a plurality of instruction streams, each of the plurality of instruction streams being equivalent; executing, in a context, a first stream of the plurality of instruction streams; stopping execution of the first stream at a first location of... Agent:
20150019846 - System level architecture verification for transaction execution in a multi-processing environment: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output... Agent:
20150019847 - Programmable cpu register hardware context swap mechanism: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to... Agent:
20150019848 - Asynchronous lookahead hierarchical branch prediction: Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a computer-implemented method for asynchronous lookahead hierarchical branch prediction using a second-level branch target buffer. The method includes receiving a search request to locate branch prediction information associated with a search address. The method further includes searching, by a... Agent:
20150019849 - Semi-exclusive second-level branch target buffer: Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a computer-implemented method for a semi-exclusive second-level branch target buffer. The method includes performing a search to locate entries in a BTB2 having a memory region corresponding to a search request. Based on locating the entries in the... Agent:Previous industry: Electrical computers and digital processing systems: memory
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