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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
12/18/2014 > 10 patent applications in 8 patent subcategories.

20140372727 - Instruction and logic to provide vector blend and permute functionality: Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a... Agent: Intel Corporation

20140372728 - Vector execution unit for digital signal processor: A vector execution unit for use in a digital signal processor enables a new set of instructions. The unit comprises a first input port for receiving at least a first input data vector, an instruction decoder, a vector output port, and least one data-path. The instruction decoding unit is arranged... Agent: Media Tek Sweden Ab

20140372729 - Processor with execution unit wait control: A processor includes a processor core. The processor core includes a first execution unit and a second execution unit. The first execution unit is configured to 1) execute a complex instruction that requires multiple instruction cycles to execute; 2) generate a wait signal that when asserted suspends execution of instructions... Agent: Texas Instruments Deutschland Gmbh

20140372731 - Data processing systems: A data processing system includes an execution pipeline that includes one or more programmable execution stages which execute execution threads to execute instructions to perform data processing operations. Instructions to be executed by a group of execution threads are first fetched into an instruction cache and then read from the... Agent:

20140372730 - Software controlled data prefetch buffering: The invention relates to the method of prefetching data in micro-processor buffer under software controls.... Agent:

20140372732 - Accelerated reversal of speculative state changes and resource recovery: A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush... Agent:

20140372733 - Processor with inter-execution unit instruction issue: A processor includes an instruction storage memory, a processor core, and an instruction merge unit. The processor core includes a plurality of execution units coupled to the instruction storage memory. A first of the execution units is configured to execute instructions provided from the instruction storage memory via a first... Agent:

20140372735 - Software controlled instruction prefetch buffering: The invention relates to the method of prefetching instruction in micro-processor buffer under software controls.... Agent:

20140372734 - User-level hardware branch records: A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to... Agent:

20140372736 - Data processing apparatus and method for handling retrieval of instructions from an instruction cache: A data processing apparatus and method are provided for handling retrieval of instructions from an instruction cache. Fetch circuitry retrieves instructions from the instruction cache into a temporary buffer, and execution circuitry executes a sequence of instructions retrieved from the temporary buffer, that sequence including branch instructions. Branch prediction circuitry... Agent:

  
12/11/2014 > 8 patent applications in 7 patent subcategories.

20140365747 - Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal partial sum of packed data elements in response to a single vector packed horizontal sum instruction that includes a destination vector register operand, a source vector register operand, and an opcode are described.... Agent:

20140365748 - Method, apparatus and system for data stream processing with a programmable accelerator: Techniques and mechanisms for programming an accelerator device to enable performance of a data processing algorithm. In an embodiment, an accelerator of a computer platform is programmed based on programming information received from a host processor of the computer platform. In another embodiment, programming of the accelerator is to enable... Agent:

20140365749 - Using a single table to store speculative results and architectural results: Some implementations provide techniques and arrangements that include a physical register file to store a speculative result of executing a operation and to store an architectural result after the operation is retired and a rename alias table to store a speculative result pointer to the speculative result stored in the... Agent:

20140365750 - Voltage droop reduction by delayed back-propagation of pipeline ready signal: A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal.... Agent:

20140365751 - Operand generation in at least one processing pipeline: A data processing apparatus has at least one processing pipeline having first, second and third pipeline stages. The first pipeline stage detects whether a stream of instructions to be processed includes a predetermined instruction sequence comprising first and second instructions for performing first and second operand generation operations, where the... Agent: Arm Limited

20140365752 - Method and system for yield operation supporting thread-like behavior: A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. A first one of a plurality of program counters is updated to point to... Agent:

20140365753 - Selective accumulation and use of predicting unit history: A microprocessor includes a predicting unit and a control unit. The control unit controls the predicting unit to accumulate a history of characteristics of executed instructions and makes predictions related to subsequent instructions based on the history while the microprocessor is running a first thread. The control unit also detects... Agent:

20140365754 - Context control and parameter passing within microcode based instruction routines: A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode... Agent:

  
12/04/2014 > 7 patent applications in 5 patent subcategories.

20140359251 - Signal processing device and signal processing method: A signal processing device including: one or more vector processors configured to perform vector processing to a signal using a parameter, one or more scalar processors configured to perform scalar processing for generating the parameter, a first circuit coupled to the one or more vector processors and the one or... Agent: Fujitsu Limited

20140359250 - Type inference for inferring scalar/vector components: Methods and systems are provided for inferring types in a computer program. In one example, a method comprises: identifying a type of at least one expression of the computer program; and annotating the at least one expression in the computer program when the type of the at least one expression... Agent: Advanced Micro Devices, Inc.

20140359252 - Digital signal processor: A multicore processor is achieved by a processor assembly, comprising a first processor having a first core and at least a first and a second unit, each being selected from the group of vector execution units, memory units and accelerators, said first core and first and second units being interconnected... Agent: Media Tek Sweden Ab

20140359253 - Increasing macroscalar instruction level parallelism: A processor may include a vector functional unit that supports concurrent operations on multiple data elements of a maximum element size. The functional unit may also support concurrent execution of multiple distinct vector program instructions, where the multiple vector instructions each operate on multiple data elements of less than the... Agent: Apple Inc.

20140359255 - Coarse-grained data processor having both global and direct interconnects: A data processor having a plurality of coarse-grained data processing elements arranged in rows and columns, an interconnect structure comprising both global and direct interconnects, the global interconnects interconnecting the coarse-grained data processing elements globally and the direct interconnects interconnecting adjacent data processing elements.... Agent: Pact Xpp Technologies Ag

20140359254 - Logical cell array and bus system: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate... Agent: Pact Xpp Technologies Ag

20140359256 - Coupled dynamical systems for chaos computing: The present invention provides systems and methods for coupled dynamical systems for chaos computing. For example, a system for the coupled dynamical system comprises a first, second, and third circuit. The first circuit comprising a plurality of single dynamical systems forms a coupled dynamical system that reduces local noises in... Agent:

  
11/27/2014 > 13 patent applications in 8 patent subcategories.

20140351556 - Methods for operating and configuring a reconfigurable processor: The invention provides a method of compiling computer program instructions for implementation on a reconfigurable processor comprising a plurality of operational cells, each operational cell being connectable to and disconnectable from one or more of the other operational cells via a programmable interconnect, the method comprising: a routing step in... Agent:

20140351557 - Processing system with interspersed processors and communication elements having improved communication routing: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output... Agent:

20140351559 - Low power management of multiple sensor chip architecture: A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, receiving, at the first processor, first sensor data from a... Agent:

20140351558 - Low power management of multiple sensor integrated chip architecture: A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, receiving, by the first processor operating at a first clock... Agent:

20140351560 - Low power management of multiple sensor integrated chip architecture: A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, performing, by the second processor, a first scan at a... Agent:

20140351561 - Microprocessor that fuses if-then instructions: A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information... Agent: Via Technologies, Inc.

20140351562 - Techniques for scheduling operations at an instruction pipeline: A dispatch stage of a processor core dispatches designated operations (e.g. load/store operations) to a temporary queue when the resources to execute the designated operations are not available. Once the resources become available to execute an operation at the temporary queue, the operation is transferred to a scheduler queue where... Agent: Advanced Micro Devices, Inc.

20140351563 - Advanced processor architecture: The present invention relates to a processor core having an execution unit comprising an arrangement of Arithmetic-Logic-Units, wherein the operation mode of the execution unit is switchable between an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic-Logic-Units such that a signal. from the register file crosses the execution... Agent: Hyperion Core Inc.

20140351566 - Moving average processing in processor and processor: A processor, which executes m number of arithmetic operations in parallel, executes a partial sum instruction which takes an i-th to (i+m−1)-th elements of an input data series as input elements, so as to obtain first vector data, executes the partial sum instruction which takes a (i+x)-th to (i+x+m−1)-th elements... Agent: Fujitsu Limited

20140351564 - Simplification of large networks and graphs: Embodiments relate to simplifying large and complex networks and graphs using global connectivity information based on calculated node centralities. An aspect includes calculating node centralities of a graph until a designated number of central nodes are detected. A percentage of the central nodes are then selected as pivot nodes. The... Agent: International Business Machines Corporation

20140351565 - System and apparatus for group floating-point inflate and deflate operations: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations... Agent: Microunity Systems Engineering, Inc.

20140351567 - Unique packed data element identification processors, methods, systems, and instructions: A method of an aspect includes receiving a unique packed data element identification instruction. The unique packed data element identification instruction indicates a source packed data having a plurality of packed data elements and indicates a destination storage location. A unique packed data element identification result is stored in the... Agent:

20140351568 - Opportunistic multi-thread method and processor: Disclosed are an opportunistic multi-thread method and processor, the method comprising the following steps: if a zeroth thread, a first thread, a second thread and a third thread all have instructions ready to be executed, then a zeroth clock period, a first clock period, a second clock period and a... Agent:

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