|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/10/2014 > 16 patent applications in 14 patent subcategories.
20140195775 - Instruction and logic to provide vector loads and stores with strides and masking functionality: Instructions and logic provide vector loads and/or stores with stride and mask functionality. Some embodiments, responsive to an instruction specifying: a set of loads, destination register, mask register, memory address, and stride length; execution units read values in the mask register, wherein fields in the mask register correspond to stride-length... Agent: Intel Corporation
20140195776 - Memory access for a vector processor: A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs)... Agent: Cognivue Corporation
20140195777 - Variable depth instruction fifos to implement simd architecture: In a particular embodiment, a method may include creating a plurality of variable depth instruction FIFOs and a plurality of data caches from a plurality of caches corresponding to a plurality of processors, where the plurality of caches and the plurality of processors correspond to MIMD architecture. The method may... Agent: International Business Machines Corporation
20140195778 - Instruction and logic to provide vector load-op/store-op with stride functionality: Instructions and logic provide vector load-op and/or store-op with stride functionality. Some embodiments, responsive to an instruction specifying: a set of loads, a second operation, destination register, operand register, memory address, and stride length; execution units read values in a mask register, wherein fields in the mask register correspond to... Agent: Intel Corporation
20140195779 - Software based application specific integrated circuit: A processing device is provided. A cluster includes a plurality of groups of processing elements. A multi-word device is connected to the processing elements within the groups. Each processing element in a particular group is in communication with all other processing elements within the particular group, and only one of... Agent: Wave Semiconductor
20140195780 - Forwarding condition information from first processing circuitry to second processing circuitry: A data processing apparatus comprises first and second processing circuitry. A conditional instruction executed by the second processing circuitry may have an outcome which is dependent on one of a plurality of sets of condition information maintained by the first processing circuitry. A first forwarding path can forward the sets... Agent:
20140195781 - Structured control instruction fetch unit: The structured control instruction fetch unit is a structured instruction stream controller that processes expand (XP), expand register indirect (XPR), loop (LOOP), and break (BRK) instructions for structured control. The fetch unit processes stop bits that mark the end of instruction blocks. Any instruction can be marked with a stop... Agent: King Fahd University Of Petroleum And Minerals
20140195782 - Method and apparatus to process sha-2 secure hashing algorithm: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to... Agent:
20140195783 - Dot product processors, methods, systems, and instructions: A method of an aspect includes receiving a dot product instruction. The dot product instruction indicates a first source packed data including at least four data elements, indicates a second source packed data including at least eight data elements, and indicates a destination storage location. A result packed data is... Agent:
20140195784 - Method, device and system for controlling execution of an instruction sequence in a data stream accelerator: Techniques and mechanisms for controlling execution of an instruction sequence in a data stream processing engine. In an embodiment, a control unit of the data stream processing engine detects that execution of a first instruction in an instruction sequence has ended. In another embodiment, the control unit determines information regarding... Agent:
20140195785 - Formal verification of a logic design: A method is provided for verification of a logic design for a processor execution unit which includes an instruction pipeline with one or more pipeline stages. The method includes: creating a design under test using at least a first and a second instance of the logic design; initializing the instruction... Agent: International Business Machines Corporation
20140195786 - Tracing speculatively executed instructions: A trace unit for generating items of trace data indicative of processing activities of a processor executing a stream of instructions, the unit includes trace circuitry for monitoring a behaviour of the processor; storage circuitry for storing current trace control data for controlling the trace circuitry; a data store for... Agent: Arm Limited
20140195787 - Tracking speculative execution of instructions for a register renaming data store: First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural... Agent: Arm Limited
20140195788 - Reducing instruction miss penalties in applications: Embodiments include systems and methods for reducing instruction cache miss penalties during application execution. Application code is profiled to determine “hot” code regions likely to experience instruction cache miss penalties. The application code can be linearized into a set of traces that include the hot code regions. Embodiments traverse the... Agent: Oracle International Corporation
20140195790 - Processor with second jump execution unit for branch misprediction: A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary... Agent:
20140195789 - Usefulness indication for indirect branch prediction training: A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used... Agent: Apple Inc.07/03/2014 > 47 patent applications in 25 patent subcategories.
20140189287 - Collapsing of multiple nested loops, methods and instructions: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction... Agent:
20140189288 - Instruction to reduce elements in a vector register with strided access pattern: A vector reduction instruction with non-unit strided access pattern is received and executed by the execution circuitry of a processor. In response to the instruction, the execution circuitry performs an associative reduction operation on data elements of a first vector register. Based on values of the mask register and a... Agent:
20140189292 - Functional unit having tree structure to support vector sorting algorithm and other algorithms: An apparatus is described having a functional unit of an instruction execution pipeline. The functional unit has a plurality of compare-and-exchange circuits coupled to network circuitry to implement a vector sorting tree for a vector sorting instruction. Each of the compare-and-exchange circuits has a respective comparison circuit that compares a... Agent:
20140189289 - Instruction for accelerating snow 3g wireless security algorithm: Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry... Agent:
20140189290 - Instruction for fast zuc algorithm processing: Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a... Agent:
20140189293 - Instructions for sliding window encoding algorithms: A processor is described having an instruction execution pipeline having a functional unit to execute an instruction that compares vector elements against an input value. Each of the vector elements and the input value have a first respective section identifying a location within data and a second respective section having... Agent:
20140189291 - Method and apparatus for integral image computation instructions: A method is described that performing an image integral calculation by creating a second vector and creating a third vector. The second vector is created by executing a first instruction that adds alternating elements of a first vector to respective neighboring elements of the first vector and presents resulting summations... Agent:
20140189294 - Systems, apparatuses, and methods for determining data element equality or sequentiality: Systems, apparatuses, and methods of performing in a computer processor broadcasting data in response to a single vector packed broadcasting instruction that includes a source writemask register operand, a destination vector register operand, and an opcode. In some embodiments, the data of the source writemask register is zero extended prior... Agent:
20140189295 - Apparatus and method of efficient vector roll operation: A machine readable storage medium containing program code is described that when processed by a processor causes a method to be performed. The method includes creating a resultant rolled version of an input vector by forming a first intermediate vector, forming a second intermediate vector and forming a resultant rolled... Agent:
20140189296 - System, apparatus and method for loop remainder mask instruction: A loop remainder mask instruction indicates a current iteration count of a loop as a first operand, an iteration limit of a loop as a second operand, and a destination. The loop contains iterations and each iteration includes a data element of the array. A processor receives the loop remainder... Agent:
20140189297 - Hetergeneous processor apparatus and method: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small... Agent:
20140189298 - Configurable ring network: A apparatus and computing device for providing a configurable ring network are provided herein. The apparatus includes logic to configure a ring processor for each of a plurality of processing elements, and logic to network each ring processor, wherein each ring processor communicates with other ring processors using a set... Agent:
20140189299 - Hetergeneous processor apparatus and method: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores;... Agent:
20140189301 - High dynamic range software-transparent heterogeneous computing element processors, methods, and systems: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload... Agent:
20140189302 - Optimal logical processor count and type selection for a given workload based on platform thermals and power budgeting constraints: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time... Agent:
20140189300 - Processing core having shared front end unit: A processor having one or more processing cores is described. Each of the one or more processing cores has front end logic circuitry and a plurality of processing units. The front end logic circuitry is to fetch respective instructions of threads and decode the instructions into respective micro-code and input... Agent:
20140189303 - Multistage module expansion system and multistage module communication method: A multistage module expansion system and multistage module communication method, applicable to a set-top box, are introduced. The system includes a master module, at least a preceding expansion module, and at least a succeeding expansion module. The master module generates and sends a control instruction to the preceding expansion module... Agent: Askey Computer Corp.
20140189304 - Bit-level register file updates in extensible processor architecture: This document discusses, among other things, systems and methods to receive an instruction to selectively update a value of one or more selected bits of a first register, to receive the one or more selected bits of the first register to be updated and one or more selected bits of... Agent: Tensilica Inc.
20140189305 - Redundant execution for reliability in a super fma alu: A system, processor and method to increase computational reliability by using underutilized portions of a data path with a SuperFMA ALU. The method allows the reuse of underutilized hardware to implement spatial redundancy by using detection during the dispatch stage to determine if the operation may be executed by redundant... Agent:
20140189306 - Enhanced loop streaming detector to drive logic optimization: An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic... Agent:
20140189309 - Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality: Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to... Agent:
20140189308 - Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality: Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data... Agent:
20140189307 - Methods, apparatus, instructions, and logic to provide vector address conflict resolution with vector population count functionality: Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store a variable second plurality of bits. A destination register has corresponding data fields, each of these... Agent:
20140189310 - Fault detection in instruction translations: In one embodiment, a method for identifying and replacing code translations that generate spurious fault events includes detecting, while executing a first native translation of target instruction set architecture (ISA) instructions, occurrence of a fault event, executing the target ISA instructions or a functionally equivalent version thereof, determining whether occurrence... Agent: Nvidia Corporation
20140189311 - System and method for performing a shuffle instruction: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data... Agent:
20140189312 - Programmable hardware accelerators in cpu: Embodiments of the present invention may include a data processing system comprising a processing execution block to execute instructions stored in an instruction queue, a programmable hardware accelerator, and a controller programmed to monitor the instruction queue to detect a first type of instructions stored in the instruction queue, reprogram... Agent:
20140189313 - Queued instruction re-dispatch after runahead: Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along... Agent: Nvidia Corporation
20140189315 - Copy-on-write buffer for restoring program code from a speculative region to a non-speculative region: An apparatus is described having an out-of-order instruction execution pipeline. The out-of-order execution pipeline has a first circuit and a second circuit. The first circuit is to hold a pointer to physical storage space where information is kept that cannot yet be confirmed as being free of potential dependencies on... Agent:
20140189314 - Real time instruction trace processors, methods, and systems: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor.... Agent:
20140189317 - Apparatus and method for a hybrid latency-throughput processor: An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program... Agent:
20140189318 - Automatic register port selection in extensible processor architecture: This document discusses, among other things, systems and methods to access n consecutive entries of a register file in a single operation using a register file entry index consisting of B bits, wherein B is less than the binary logarithm of a depth of the register file, which corresponds to... Agent: Tensilica Inc.
20140189316 - Execution pipeline data forwarding: In one embodiment, in an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit is provided. The method includes producing output data with the producing execution subunit, consuming input data... Agent: Nvidia Corporation
20140189319 - Opportunistic utilization of redundant alu: A processor includes at least one processing core that includes an operation dispatch for dispatching operations from an instruction pipeline, a plurality of arithmetic logic units for executing the operations, a plurality of multiplexers, each of which connects the operation dispatch to a respective arithmetic logic unit, and a controller... Agent:
20140189320 - Instruction for determining histograms: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry... Agent:
20140189321 - Instructions and logic to vectorize conditional loops: Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to specify a conditions mask register, and a destination parameter to specify a destination vector to hold n consecutive vector elements, each of the plurality of n consecutive... Agent:
20140189322 - Systems, apparatuses, and methods for masking usage counting: Embodiments of systems, apparatuses, and methods for counting instructions of a particular type are described herein. In some embodiments, a processor includes a plurality of write mask registers, logic to determine write mask register usage of an instruction in a particular manner and a counter to count a number of... Agent:
20140189323 - Apparatus and method for propagating conditionally evaluated values in simd/vector execution: An apparatus and method for propagating conditionally evaluated values. For example, a method according to one embodiment comprises: reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; for each true value read from... Agent:
20140189327 - Acknowledgement forwarding: A method for processing data packets in a pipeline and executed by a network processor. The pipeline includes a plurality of logical blocks, each logical block configured to process one stage of the pipeline. Each data packet includes a descriptor and a data. The network processor is coupled to a... Agent: Telefonaktiebolaget L M Ericsson (publ)
20140189326 - Memory management in secure enclaves: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of... Agent:
20140189325 - Paging in secure enclaves: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting... Agent:
20140189324 - Physical register table for eliminating move instructions: Embodiments of an invention for a physical register table for eliminating move instructions are disclosed. In one embodiment, a processor includes a physical register file, a register allocation table, and a physical register table. The register allocation table is to store mappings of logical registers to physical registers. The physical... Agent:
20140189329 - Cooperative thread array granularity context switch during trap handling: Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during... Agent: Nvidia Corporation
20140189328 - Power reduction by using on-demand reservation station size: A computer processor, a computer system and a corresponding method involve a reservation station that stores instructions which are not ready for execution. The reservation station includes a storage area that is divided into bundles of entries. Each bundle is switchable between an open state in which instructions can be... Agent:
20140189330 - Optional branches: Branch instructions are provided for improved execution performance. The branch instruction includes one or more paths that are marked as a safe path for execution. If a marked path is executed based on a branch prediction, the execution continues until completion after it is determined that the other path is... Agent:
20140189331 - System of improved loop detection and execution: An method may include identifying loop information corresponding to a plurality of loop instructions. The loop instructions are stored into a queue. The loop instructions are replayed from the queue for execution. Loop iteration is counted based on the identified loop information. A determination of whether the last iteration of... Agent:
20140189332 - Apparatus and method for low-latency invocation of accelerators: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why... Agent:
20140189333 - Apparatus and method for task-switchable synchronous hardware accelerators: A processor comprising: execution logic to execute a first thread including an accelerator invocation instruction to invoke an accelerator command; an accelerator to execute an accelerator thread in response to the accelerator command, the accelerator to store state data associated with the accelerator thread in a application memory area in... Agent:06/26/2014 > 21 patent applications in 17 patent subcategories.
20140181466 - Processors having fully-connected interconnects shared by vector conflict instructions and permute instructions: An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least... Agent:
20140181467 - High level software execution mask override: Methods, and media, and computer systems are provided. The method includes, the media includes control logic for, and the computer system includes a processor with control logic for overriding an execution mask of SIMD hardware to enable at least one of a plurality of lanes of the SIMD hardware. Overriding... Agent: Advanced Micro Devices, Inc.
20140181468 - Register files for a digital signal processor operating in an interleaved multi-threaded environment: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of... Agent: Qualcomm Incorporated
20140181469 - Methods and apparatus for reducing power consumption within embedded systems: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and... Agent:
20140181471 - Adaptive data collection practices in a multi-processor device: Adaptive data collection practices in a multi-processor device. The device may include a first processor and a second processor. The first processor may operate in any of a plurality of power states. The first processor may indicate to the second processor when it transitions to a different power state. The... Agent: Apple Inc.
20140181470 - Parallel processing using multi-core processor: Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of multi-threaded core processors and special purpose processors for processing the data packets atomically, and in parallel. An ingress module of the network processor... Agent: Unbound Networks, Inc.
20140181472 - Scalable compute fabric: A method and apparatus for providing a scalable compute fabricare provided herein. The method includes determining a workflow for processing by the scalable compute fabric, wherein the workflow is based on an instruction set. A pipeline in configured dynamically for processing the workflow, and the workflow is executed using the... Agent:
20140181473 - System and method for implementing shared probabilistic counters storing update probability values: The systems and methods described herein may implement probabilistic counters and/or update mechanisms for those counters such that they are dependent on the value of a configurable accuracy parameter. The accuracy parameter value may be adjusted to provide fine-grained control over the tradeoff between the accuracy of the counters and... Agent: Oracle International Corporation
20140181474 - Atomic write and read microprocessor instructions: Methods and apparatus for performing an atomic hardware operation (HWOP) instruction. According to a method in a computer processor coupled to a memory, the method includes fetching, decoding, and executing the atomic HWOP instruction. The instruction includes a source operand indicating a source location and a destination operand indicating a... Agent: Telefonaktiebolaget L M Ericsson (publ)
20140181475 - Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines: A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instruction formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.... Agent: Soft Machines, Inc.
20140181477 - Compressing execution cycles for divergent execution in a single instruction multiple data (simd) processor: In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor... Agent:
20140181476 - Scheduler implementing dependency matrix having restricted entries: A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded... Agent:
20140181478 - Dynamic write port re-arbitration: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required.... Agent: Arm Limited
20140181479 - Method, apparatus, system creating, executing and terminating mini-threads: Described herein are mechanisms for creating, executing, and terminating mini-threads. A processor executes instructions with a primary thread in a first execution mode, and to execute an instruction to create a secondary mini-thread that is associated with a first subset of registers and associates the primary thread with a second... Agent:
20140181480 - Nested speculative regions for a synchronization facility: An apparatus, computer readable medium, and method of performing nested speculative regions are presented. The method includes responding to entering a speculative region by storing link information to an abort handler and responding to a commit command by removing link information from the abort handler. The method may include storing... Agent: Advanced Micro Devices, Inc.
20140181481 - Detection of potential need to use a larger data format in performing floating point operations: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.... Agent: International Business Machines Corporation
20140181483 - Computation memory operations in a logic layer of a stacked memory: Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic... Agent: Advanced Micro Devices, Inc.
20140181482 - Store-to-load forwarding: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted... Agent: Advanced Micro Devices, Inc.
20140181484 - Mechanism to provide high performance and fairness in a multi-threading computer system: According to one embodiment, a processor includes an execution pipeline for executing a plurality of threads, including a first thread and a second thread. The processor further includes a multi-thread controller (MTC) coupled to the execution pipeline to determine whether to switch threads between the first and second thread based... Agent:
20140181485 - Sticky bit update within a speculative execution processing environment: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed... Agent: Arm Limited
20140181486 - Branch prediction table install source tracking: Embodiments relate to branch prediction table install source tracking. An aspect includes a computer-implemented method for branch prediction table install source tracking. The method includes receiving at a branch target buffer a request to install a branch target buffer entry corresponding to a branch instruction for branch prediction. The method... Agent: International Business Machines Corporation06/19/2014 > 17 patent applications in 12 patent subcategories.
20140173246 - Scheduling application instances to configurable processing cores based on application requirements and resource specification: Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs),... Agent:
20140173247 - Processing apparatus and method of synchronizing a first processing unit and a second processing unit: A processing apparatus, comprising at least a first processing unit and a second processing unit, is proposed. The first processing unit comprises a set of first stateful elements, the second processing unit comprises a set of second stateful elements. A set of synchronization data lines may connect the first stateful... Agent: Freescale Semiconductor, Inc.
20140173248 - Performing frequency coordination in a multiprocessor system based on response timing optimization: In an embodiment, a processor includes a core to execute instructions and a logic to receive memory access requests from the core and to route the memory access requests to a local memory and to route snoop requests corresponding to the memory access requests to a remote processor. The logic... Agent:
20140173250 - Selection of a primary microprocessor for initialization of a multiprocessor system: Embodiments of the present invention provide a method for initializing a plurality of processors of a multi-processor system by executing, at each respective processor of the plurality of processors, at least a portion of local initialization code stored on the respective processor. Receiving, at a designated processor of the plurality... Agent: International Business Machines Corporation
20140173251 - Selection of a primary microprocessor for initialization of a multiprocessor system: Embodiments of the present invention provide a method for initializing a plurality of processors of a multi-processor system by executing, at each respective processor of the plurality of processors, at least a portion of local initialization code stored on the respective processor. Receiving, at a designated processor of the plurality... Agent: International Business Machines Corporation
20140173249 - System and method for connecting a system on chip processor and an external processor: A system and method are provided for connecting a system on chip (SoC) processor and an external processor. The SoC processor receives as input a content stream, and processes the content stream. Further, the application processor that is connected to the SoC processor receives the processed content stream, performs further... Agent: Nvidia Corporation
20140173252 - System-on-chip design structure and method: Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The... Agent: Fujitsu Limited
20140173253 - Methods and apparatus for storing expanded width instructions in a vliw memory for deferred execution: Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a... Agent: Altera Corporation
20140173254 - Cache prefetch for deterministic finite automaton instructions: In a DFA scanning engine used to match regular expressions or similar rules, instructions to execute DFA state transitions are accessed through an instruction cache. Each DFA instruction may indicate varying numbers of transitions or branches from a current state. The cache pre-fetches a requested number of additional instructions consecutively... Agent: Lsi Corporation
20140173255 - Instruction set for supporting wide scalar pattern matches: A processor includes an instruction decoder to receive an instruction having a first operand, a second operand, and a third operand, and an execution unit coupled to the instruction decoder to execute the instruction, the execution unit to individually perform a shift operation by at least one bit for each... Agent:
20140173256 - Processor configured for operation with multiple operation codes per instruction: A method of associating operation codes with instructions for execution in a processor includes the steps of assigning the operation codes to the instructions in a manner that allows a given instruction to have multiple assigned operation codes and selecting a particular one of the multiple assigned operation codes for... Agent: Lsi Corporation
20140173257 - Requesting shared variable directory (svd) information from a plurality of threads in a parallel computer: Methods, parallel computers, and computer program products for requesting shared variable directory (SVD) information from a plurality of threads in a parallel computer are provided. Embodiments include a runtime optimizer detecting that a first thread requires a plurality of updated SVD information associated with shared resource data stored in a... Agent: International Business Machines Corporation
20140173258 - Technique for performing memory access operations via texture hardware: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on... Agent: Nvidia Corporation
20140173259 - Computer processor with instruction for execution based on available instruction sets: A system and method for testing whether a computer processor is capable of executing a requested instruction set. The system includes a computer processor configured to receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implement the encoded conditional branch... Agent: International Business Machines Corporation
20140173260 - Computer processor with instruction for execution based on available instruction sets: A system and method for testing whether a computer processor is capable of executing a requested instruction set. The system includes a computer processor configured to receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implement the encoded conditional branch... Agent: International Business Machines Corporation
20140173261 - Computer processor with instruction for execution based on available instruction sets: A system and method for testing whether a computer processor is capable of executing a requested instruction set. The system includes a computer processor configured to receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implement the encoded conditional branch... Agent: International Business Machines Corporation
20140173262 - Energy-focused compiler-assisted branch prediction: A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.... Agent: Bluerisc Inc.Previous industry: Electrical computers and digital processing systems: memory
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