|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/04/2014 > 3 patent applications in 3 patent subcategories.
20140250287 - Information processing device, job scheduling method, and job scheduling program: An information processing device includes: a measurement unit 10 for measuring respective use rates of a plurality of coprocessors each for executing a job, respective use rates of a plurality of interface cards each for passing data input or output by each of the plurality of coprocessors, and respective latencies... Agent: Nec Corporation
20140250288 - Systems and methods that formulate embeddings of problems for solving by a quantum processor: Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to... Agent: D-wave Systems Inc.
20140250289 - Branch target buffer with efficient return prediction capability: Improved branch target buffers (BTBs) and methods of processing data in a microprocessor with a pipeline are provided. According to various embodiments, a BTB is provided that includes a non-return buffer, a return buffer, and a multiplexer. The non-return buffer is designed to store a multiple of non-return entries. Each... Agent: Mips Technologies, Inc.08/28/2014 > 21 patent applications in 16 patent subcategories.
20140244968 - Mapping vector representations onto a predicated scalar multi-threaded system: A system implementing a method for generating code for execution based on a SIMT model with parallel units of threads is provided. The system identifies a loop within a program that includes vector processing. The system generates instructions for a thread that include an instruction to set a predicate based... Agent:
20140244967 - Vector register addressing and functions based on a scalar register data value: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified, in a... Agent: Qualcomm Incorporated
20140244970 - Digital signal processor and baseband communication device: c
20140244969 - List vector processing apparatus, list vector processing method, storage medium, compiler, and information processing apparatus: The LVPA includes: a gather processing unit processing a first gather instruction to store a value of a storage area accessed by only a self information processing apparatus (SelfIPA) in a plurality of information processing apparatuses according to a list vector storing an address representing a storage area read from... Agent: Nec Corporation
20140244971 - Array of processor core circuits with reversible tiers: Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets... Agent: International Business Machines Corporation
20140244972 - Method and apparatus for game physics concurrent computations: An apparatus for physical properties computation comprising an array processor. The array processor comprises of a plurality of processing elements, said processing elements arranged in a grid. A processing unit (PU) is coupled to the array processor. A local memory is coupled to the PU. The PU broadcasts data to... Agent: Aiseek Ltd.
20140244973 - Reconfigurable elements: The present invention provides for a multiprocessor device on either a chip or a stack of chips. The multiprocessor device includes a plurality of processing entities and a memory system. The multiprocessor device further includes at least one interface unit to at least one of an external memory and one... Agent: Pact Xpp Technologies Ag
20140244974 - Background collective operation management in a parallel computer: Background collective operation management in a parallel computer, the parallel computer including one or more compute nodes operatively coupled for data communications over one or more data communications networks, including: determining, by a management availability module, whether a compute node in the parallel computer is available to perform a background... Agent: International Business Machines Corporation
20140244975 - Multi-core processor, controlling method thereof and computer system with such processor: A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M.... Agent: Rdc Semiconductor Co., Ltd.
20140244976 - It instruction pre-decode: Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within... Agent: Apple Inc.
20140244977 - Deferred saving of registers in a shared register pool for a multithreaded microprocessor: A method of sharing a plurality of registers in a register pool among a plurality of microprocessor threads begins by allocating a first set of registers in the register pool to a first thread, the first thread executing a first instruction using the first set of registers in the register... Agent: Mips Technologies, Inc.
20140244978 - Checkpointing registers for transactional memory: The present invention provides a method and apparatus for checkpointing registers for transactional memory. Some embodiments of the apparatus include first rename logic configured to map up to a predetermined number of architectural registers to corresponding first physical registers that hold first values associated with the architectural registers. The mapping... Agent: Advanced Micro Devices, Inc.
20140244979 - Estimating time remaining for an operation: Techniques for estimating time remaining for an operation are described. Examples operations include file operations, such as file move operations, file copy operations, and so on. A wide variety of different operations may be considered in accordance with the claimed embodiments, further examples of which are discussed below. In at... Agent: Microsoft Corporation
20140244980 - Method and system for dynamic control of a multi-tier processing system: Method, system, and programs for dynamic control of a processing system having a plurality of tiers. Queue lengths of a plurality of nodes in one of the plurality of tiers are received. A control objective is received from a higher tier. One or more requests from the higher tier are... Agent:
20140244981 - Processor and control method for processor: A processor includes a programmable logic circuit provided with a plurality of processing units. The programmable logic circuit is capable of reconfiguring a first logic circuit corresponding to first circuit configuration information according to a first process and a second logic circuit corresponding to second circuit configuration information according to... Agent: Fujitsu Semiconductor Limited
20140244982 - Performing stencil computations: A method and apparatus for performing stencil computations efficiently are disclosed. In one embodiment, a processor receives an offset, and in response, retrieves a value from a memory via a single instruction, where the retrieving comprises: identifying, based on the offset, one of a plurality of registers of the processor;... Agent:
20140244984 - Eligible store maps for store-to-load forwarding: The present invention provides a method and apparatus for generating eligible store maps for store-to-load forwarding. Some embodiments of the method include generating information associated with a load instruction in a load queue. The information indicates whether one or more store instructions in a store queue is older than the... Agent: Advanced Micro Devices, Inc.
20140244983 - Executing an operating system on processors having different instruction set architectures: An apparatus includes a first processor having a first instruction set and a second processor having a second instruction set that is different than the first instruction set. The apparatus also includes a memory storing at least a portion of an operating system. The operating system is concurrently executable on... Agent: Qualcomm Incorporated
20140244985 - Intelligent context management: Intelligent context management for thread switching is achieved by determining that a register bank has not been used by a thread for a predetermined number of dispatches, and responsively disabling the register bank for use by that thread. A counter is incremented each time the thread is dispatched but the... Agent: International Business Machines Corporation
20140244986 - System and method to select a packet format based on a number of executed threads: A system and method to select a packet format based on a number of executed threads is disclosed. In a particular embodiment, a method includes determining, at a multi-threaded processor, a number of threads of a plurality of threads executing during a time period. A packet format is determined from... Agent: Qualcomm Incorporated
20140244987 - Precision exception signaling for multiple data architecture: Methods and systems that perform one or more operations on a plurality of elements using a multiple data processing element processor are provided. An input vector comprising a plurality of elements is received by a processor. The processor determines if performing a first operation on a first element will cause... Agent: Mips Technologies, Inc.08/21/2014 > 7 patent applications in 6 patent subcategories.
20140237213 - High dose radiation detector: Described is a processor comprising: a plurality of radiation detectors; a first logic unit to receive outputs from the plurality of radiation detectors, the logic unit to generate an output according to the received outputs, the output of the first logic unit indicating whether the processor was exposed to incoming... Agent:
20140237214 - Apparatus and method of a concurrent data transfer of multiple regions of interest (roi) in an simd processor system: This present invention provides a fast data transfer for a concurrent transfer of multiple ROI areas between an internal memory array and a single memory where each PE can specify the parameter set for the area to be transferred independently from the other PE. For example, for a read transfer,... Agent: Renesas Electronics Corporation
20140237215 - Methods and apparatus for scalable array processor interrupt detection and response: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When... Agent: Altera Corporation
20140237216 - Microprocessor: A microprocessor according to an aspect of the present invention includes an arithmetic operation unit. The arithmetic operation unit includes: a plurality of arithmetic operation devices arranged in a multi-stage arrangement; a delay device provided to each stage of the arithmetic operation devices excluding a final stage, and configured to... Agent: Casio Computer Co., Ltd.
20140237218 - Simd integer multiply-accumulate instruction for multi-precision arithmetic: A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second... Agent:
20140237217 - Vectorization in an optimizing compiler: An optimizing compiler includes a vectorization mechanism that optimizes a computer program by substituting code that includes one or more vector instructions (vectorized code) for one or more scalar instructions. The cost of the vectorized code is compared to the cost of the code with only scalar instructions. When the... Agent: International Business Machines Corporation
20140237219 - Microstackshots: A method and apparatus of a device that captures a stackshot of an executing process is described. In an exemplary embodiment, the device detects an interrupt of the process occurring during the execution of the process, where the process execution can be in a kernel space and user space, and... Agent: Apple Inc.08/14/2014 > 18 patent applications in 10 patent subcategories.
20140229705 - Analog processor comprising quantum devices: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device.... Agent: D-wave Systems Inc.
20140229704 - Precise-restartable parallel execution of programs: Interrupt handling on a multiprocessor computer executing multiple computational operations in parallel is provided by establishing a total ordering of the multiple computational operations and defining an architectural state at the time of the interrupt as if the computational operations executed in the total ordering.... Agent: Wisconsin Alumni Research Founddation
20140229706 - Dynamic thread status retrieval using inter-thread communication: A circuit arrangement, method, and program product for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources.... Agent: International Business Machines Corporation
20140229707 - Electronics apparatus able to revise micro-program and algorithm to revise micro-program: An electronic apparatus is disclosed, where the apparatus revises the micro-program thereof reliably. The apparatus provides a master and slave CPUs each having a memory. The micro-program to be revised is temporarily set in the memory of the slave CPU. Interrupting the master CPU, and connecting the slave CPU with... Agent: Sumitomo Electric Industries, Ltd.
20140229709 - Dynamic thread status retrieval using inter-thread communication: A circuit arrangement, method, and program product for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources.... Agent: International Business Machines Corporation
20140229708 - Extensible execution unit interface architecture: A method and circuit arrangement tightly couple together decode logic associated with multiple types of execution units and having varying priorities to enable instructions that are decoded as valid instructions for multiple types of execution units to be forwarded to a highest priority type of execution unit among the multiple... Agent: International Business Machines Corporation
20140229710 - Local instruction loop buffer utilizing execution unit register file: A method and circuit arrangement utilize a register file of an execution unit as a local instruction loop buffer to enable suitable algorithms, such as DSP algorithms, to be fetched and executed directly within the execution unit, and often enabling other logic circuits utilized for other, general purpose workloads to... Agent: International Business Machines Corporation
20140229713 - Extensible execution unit interface architecture: A method and circuit arrangement tightly couple together decode logic associated with multiple types of execution units and having varying priorities to enable instructions that are decoded as valid instructions for multiple types of execution units to be forwarded to a highest priority type of execution unit among the multiple... Agent: International Business Machines Corporation
20140229711 - Indirect instruction predication: A method, circuit arrangement, and program product for selectively predicating instructions in an instruction stream by determining a first register address from an instruction, determining a second register address based on a value stored at the first register address, and determining whether to predicate the instruction based at least in... Agent: International Business Machines Corporation
20140229712 - Indirect instruction predication: A method, circuit arrangement, and program product for selectively predicating instructions in an instruction stream by determining a first register address from an instruction, determining a second register address based on a value stored at the first register address, and determining whether to predicate the instruction based at least in... Agent: International Business Machines Corporation
20140229714 - Local instruction loop buffer utilizing execution unit register file: A method and circuit arrangement utilize a register file of an execution unit as a local instruction loop buffer to enable suitable algorithms, such as DSP algorithms, to be fetched and executed directly within the execution unit, and often enabling other logic circuits utilized for other, general purpose workloads to... Agent: International Business Machines Corporation
20140229715 - Apparatus and method for providing eventing ip and source data address in a statistical sampling infrastructure: A processor includes a core that includes an execution engine unit for executing instructions, a controller, and a storage having stored thereon a statistical sampling record, in which in response to occurrence of a hardware event caused by executing an instruction, the controller is configured to: (1) determine an instruction... Agent:
20140229716 - Vector and scalar based modular exponentiation: An embodiment includes a method for computing operations, such as modular exponentiation, using a mix of vector and scalar instructions to accelerate various applications such as encryption protocols that rely heavily on large number arithmetic operations. The embodiment requires far fewer instructions to execute the operations than more conventional practices.... Agent:
20140229717 - Binary translator driven program state relocation: This disclosure is directed to binary translator driven program state relocation. In general, a device may protect vulnerable program functions by setting them as non-executable. If an attempt is made to execute a protected program function, the program may trap to a binary translator in the device that may be... Agent:
20140229718 - Speculative load issue: A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store... Agent: Imagination Technologies, Ltd.
20140229719 - Method and apparatus for branch prediction: A branch prediction unit BPU (500) for prediction of a next taken branch instruction in a processing unit (100). The BPU (500) comprises a pattern history memory (504) comprising branch source addresses and branch indicators; a branch target buffer (506) comprising branch targets; and branch prediction logical circuit (502). By... Agent: Ericsson Moderns Sa
20140229720 - Branch prediction with power usage prediction and control: A method and circuit arrangement maintain power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that... Agent: International Business Machines Corporation
20140229721 - Dynamic branch hints using branches-to-nowhere conditional branch: A processor includes an execution pipeline having one or more execution units to execution the instructions and a branch prediction unit coupled to the execution units. The branch prediction unit includes a branch history table to store prior branch predictions, a branch predictor, in response to a conditional branch instruction,... Agent:Previous industry: Electrical computers and digital processing systems: memory
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