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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
06/11/2015 > patent applications in patent subcategories.
  
06/04/2015 > patent applications in patent subcategories.
  
05/28/2015 > 4 patent applications in 4 patent subcategories.

20150149744 - Data processing apparatus and method for performing vector processing: A data processing apparatus and method are provided for processing execution threads, where each execution thread specifies at least one instruction. The data processing apparatus has a vector processing unit providing a plurality M of lanes of parallel processing, within each lane the vector processing unit being configured to perform... Agent:

20150149745 - Parallelization with controlled data sharing: In one general aspect, a method can include executing multiple functions calls in parallel, and receiving, by each function call, at least one data object passed as a parameter to the function call, the at least one data object associated with a data sharing mode that defines a restricted subset... Agent:

20150149746 - Arithmetic processing device, information processing device, and a method of controlling the information processing device: An arithmetic processing device promotes transmission efficiency between a processor and a memory. The arithmetic processing device has an arithmetic processing unit which issues an instruction accompanying with data which is sent to the memory, a judgment unit which judges whether or not a redundancy degree of the data which... Agent:

20150149747 - Method of scheduling loops for processor having a plurality of functional units: Provided is a loop scheduling method including scheduling a first loop using execution units, and scheduling a second loop using execution units available as a result of the scheduling of the first loop. An n-th loop (n>2) may be scheduled using a result of scheduling an (n−1)-th loop, similar to... Agent: Samsung Electronics Co., Ltd.

  
05/21/2015 > 17 patent applications in 10 patent subcategories.

20150143073 - Data processing systems: A data processing system is described in which a plurality of data processing units 521 . . . 52N cooperate with one another in order to process incoming data packets or an incoming data stream. Tasks are managed using a task list which is accessible and updateable by each data... Agent: Bluwireless Technology Limited

20150143074 - Vector exception code: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The... Agent:

20150143075 - Vector generate mask instruction: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the... Agent:

20150143080 - Vector checksum instruction: Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out... Agent:

20150143078 - Vector processing engines (vpes) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption are disclosed. Related vector processor systems and methods are also disclosed. The VPEs are configured to provide filter vector processing operations. To minimize re-fetching of input vector data... Agent: Qualcomm Incorporated

20150143076 - Vector processing engines (vpes) employing despreading circuitry in data flow paths between execution units and vector data memory to provide in-flight despreading of spread-spectrum sequences, and related vector processing instructions, systems, and meth: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow... Agent: Qualcomm Incorporated

20150143077 - Vector processing engines (vpes) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory, and related vector processing instructions, sys: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow... Agent: Qualcomm Incorporated

20150143079 - Vector processing engines (vpes) employing tapped-delay line(s) for providing precision correlation / covariance vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision correlation/covariance vector processing operations with reduced sample re-fetching and/or power consumption are disclosed. The VPEs disclosed herein are configured to provide correlation/covariance vector processing operations, such as code division multiple access (CDMA) correlation/covariance vector processing operations as a non-limiting... Agent: Qualcomm Incorporated

20150143081 - Processor capable of supporting multimode and multimode supporting method thereof: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence,... Agent: Samsung Electronics Co., Ltd.

20150143082 - Dynamically erectable computer system: A fault-tolerant computer system architecture includes two types of operating domains: a conventional first domain (DID) that processes data and instructions, and a novel second domain which includes mentor processors for mentoring the DID according to “meta information” which includes but is not limited to data, algorithms and protective rule... Agent:

20150143083 - Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction: Techniques for increasing vector processing utilization and efficiency through use of unmasked lanes of predicated vector instructions for executing non-conflicting instructions are provided. In one aspect, a method of vector lane predication for a processor is provided which includes the steps of: fetching predicated vector instructions from a memory; decoding... Agent: International Business Machines Corporation

20150143084 - Hand held device to perform a bit range isolation instruction: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value... Agent: Intel Corporation

20150143087 - Service system and method: A system includes provision of a first set of instructions associated with a product to a user of the product, the user having one or more associated characteristics, reception of a revision to the first set of instructions from the user, determination of whether to modify the first set of... Agent: General Electric Company

20150143088 - Vector element rotate and insert under mask instruction: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the... Agent:

20150143086 - Vector processing engines (vpes) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations, and r: Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided... Agent: Qualcomm Incorporated

20150143085 - Vector processing engines (vpes) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory, and related vector processor systems and: Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths... Agent: Qualcomm Incorporated

20150143089 - System performance enhancement with smi on multi-core systems: Mechanisms for providing enhanced system performance and reliability on multi-core computing devices are discussed. Embodiments use modified hardware and/or software so that when a System Management Interrupt (SMI#) is generated, only a single targeted CPU core enters System Management Mode (SMM) in response to the SMI while the remaining CPU... Agent:

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