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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
01/22/2015 > 14 patent applications in 10 patent subcategories.

20150026433 - Allocation method, apparatus, and program for architectural register: An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register... Agent:

20150026432 - Dynamic formation of symmetric multi-processor (smp) domains: Symmetric multi-processor (SMP) nodes are dynamically configured via SMP sockets that use SMP optically-connected switches to dynamically connect SMP optically-connected links connected to the SMP nodes to form SMP domains based on best matched expected workloads for coherent traffic for exchanging SMP coherent information. The SMP nodes are dynamically added... Agent:

20150026434 - Configurable logic constructs in a loop buffer: Techniques are described herein for using configurable logic constructs in a loop buffer. In an embodiment, a configurable hardware block is programmed based on one or more target functions within a loop. The configurable hardware block is associated with a plurality of registers, including a loopcount register and a first... Agent: Oracle International Corporation

20150026435 - Instruction set architecture with extensible register addressing: A method and circuit arrangement selectively source and/or write data from/to extended registers of an extended register file based in part on whether an operand address of an instruction references a primary register of primary register file configured to store a pointer to the extended register. Control logic connected to... Agent: International Business Machines Corporation

20150026436 - Hybrid tag scheduler: The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry... Agent: Advanced Micro Devices, Inc.

20150026437 - Method and apparatus for differential checkpointing: A processor core stores information that maps a physical register to an architectural register in response to an instruction modifying the architectural register. The processor recovers a checkpointed state of a set of architectural registers prior to modification of the architectural register by the instruction by modifying a reference mapping... Agent:

20150026438 - System, method, and computer program product for cooperative multi-threading for vector threads: A system, method, and computer program product for ensuring forward progress of threads that implement divergent operations in a single-instruction, multiple data (SIMD) architecture is disclosed. The method includes the steps of allocating a queue data structure to a thread block including a plurality of threads, determining that a current... Agent:

20150026440 - Apparatus and method for performing a permute operation: An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for... Agent:

20150026439 - Apparatus and method for performing permute operations: An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for... Agent:

20150026441 - Method and system of inserting marking values used to correlate trace data as between processor cores: A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising... Agent: Texas Instruments Incorporated

20150026442 - System, method, and computer program product for managing out-of-order execution of program instructions: A method, system and computer program product embodied on a computer-readable medium are provided for managing the execution of out-of-order instructions. The method includes the steps of receiving a plurality of instructions and identifying a subset of instructions in the plurality of instructions to be executed out-of-order.... Agent: Nvidia Corporation

20150026443 - Branching to alternate code based on runahead determination: The description covers a system and method for operating a micro-processing system having a runahead mode of operation. In one implementation, the method includes providing, for a first portion of code, a runahead correlate. When the first portion of code is encountered by the micro-processing system, a determination is made... Agent:

20150026444 - Compiler-control method for load speculation in a statically scheduled microprocessor: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load... Agent:

20150026445 - Processor testing: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second... Agent:

  
01/15/2015 > 15 patent applications in 12 patent subcategories.

20150019835 - Predication methods for vector processors: A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.... Agent:

20150019836 - Register file structures combining vector and scalar data with global and local accesses: The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths... Agent:

20150019837 - Data processor: A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers... Agent:

20150019838 - Vector load and duplicate operations: A method of loading and duplicating scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.... Agent:

20150019839 - Determining processor offsets to synchronize processor time values: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A... Agent:

20150019840 - Highly integrated scalable, flexible dsp megamodule architecture: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to... Agent:

20150019841 - Anticipated prefetching for a parent core in a multi-core chip: Embodiments relate to prefetching data on a chip having a scout core and a parent core coupled to the scout core. A method includes determining that a program executed by the parent core requires content stored in a location remote from the parent core. The method includes sending a fetch... Agent:

20150019842 - Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in dsss cellular systems: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real... Agent:

20150019843 - Method and apparatus for selective renaming in a microprocessor: A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed... Agent: Qualcomm Incorporated

20150019845 - Method to extend the number of constant bits embedded in an instruction set: The invention allows a processor to maintain a fixed instruction width regardless of the width of the constants needed. The constant extension solves the problem of having variable length opcodes to accommodate longer constants. The invention allows the architecture to have a fixed width, regardless of the width of the... Agent:

20150019844 - Synthetic processing diversity within a homogeneous processing environment: A method of increasing processing diversity on a computer system includes: loading a plurality of instruction streams, each of the plurality of instruction streams being equivalent; executing, in a context, a first stream of the plurality of instruction streams; stopping execution of the first stream at a first location of... Agent:

20150019846 - System level architecture verification for transaction execution in a multi-processing environment: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output... Agent:

20150019847 - Programmable cpu register hardware context swap mechanism: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to... Agent:

20150019848 - Asynchronous lookahead hierarchical branch prediction: Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a computer-implemented method for asynchronous lookahead hierarchical branch prediction using a second-level branch target buffer. The method includes receiving a search request to locate branch prediction information associated with a search address. The method further includes searching, by a... Agent:

20150019849 - Semi-exclusive second-level branch target buffer: Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a computer-implemented method for a semi-exclusive second-level branch target buffer. The method includes performing a search to locate entries in a BTB2 having a memory region corresponding to a search request. Based on locating the entries in the... Agent:

  
01/08/2015 > 11 patent applications in 10 patent subcategories.

20150012723 - Processor using mini-cores: A mini-core and a processor using such a mini-core are provided in which functional units of the mini-core are divided into a scalar domain processor and a vector domain processor. The processor includes at least one such mini-core, and all or a portion of functional units from among the functional... Agent: Samsung Electronics Co., Ltd.

20150012724 - Data processing apparatus having simd processing circuitry: A data processing apparatus has permutation circuitry for performing a permutation operation for changing a data element size or data element positioning of at least one source operand to generate first and second SIMD operands, and SIMD processing circuitry for performing a SIMD operation on the first and second SIMD... Agent:

20150012725 - Method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations: A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores... Agent:

20150012726 - Loop streaming detector for standard and complex instruction types: A processor includes a microcode storage comprising a plurality of microcode flows and a decode logic coupled to the microcode storage. The decode logic is configured to receive a first instruction, decode the first instruction into an entry point vector to a first microcode flow in the microcode storage, the... Agent:

20150012727 - Processing device and control method of processing device: A processing device has: a plurality of registers configured to correspond to a plurality of accessible register windows; and an instruction decoder configured to inhibit, when, during an execution of a first instruction of changing a number of a current register window by one, a second instruction of changing the... Agent: Fujitsu Limited

20150012728 - System for providing trace data in a data processor having a pipelined architecture: The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the... Agent: Imagination Technologies Limited

20150012729 - Method and system of compiling program code into predicated instructions for excution on a processor without a program counter: A predicated instruction compilation system includes a control flow graph generation module to generate a control flow graph of a program code to be compiled into the predicated instructions to be executed on a processor that does not include any program counter. Each of the instructions includes a predicate guard... Agent:

20150012730 - Compact linked-list-based multi-threaded instruction graduation buffer: A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values generated by an instruction decode and dispatch unit of the processor... Agent:

20150012731 - Distribution of tasks among asymmetric processing elements: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.... Agent:

20150012732 - Method and device for recombining runtime instruction: A method for recombining runtime instruction comprising: an instruction running environment is buffered; the machine instruction segment to be scheduled is obtained; the second jump instruction which directs an entry address of an instruction recombining platform is inserted before the last instruction of the obtained machine instruction segment to generate... Agent: Beijing Zhongtian Antai Technology Co., Ltd.

20150012733 - System and method for performing deterministic processing: A system and method is provided for performing deterministic processing on a non-deterministic computer system. In one example, the system forces execution of one or more computer instructions to execute within a constant execution time. A deterministic engine, if necessary, waits a variable amount of time to ensure that the... Agent:

  
01/01/2015 > 23 patent applications in 16 patent subcategories.

20150006847 - Apparatus and method to reserve and permute bits in a mask register: An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data... Agent:

20150006848 - Multiple register memory access instructions, processors, methods, and systems: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The... Agent:

20150006849 - Reconfigurable apparatus for hierarchical collective networks with bypass mode: A reconfigurable tree apparatus with a bypass mode and a method of using the reconfigurable tree apparatus are disclosed. The reconfigurable tree apparatus uses a short-circuit register to selectively designate participating agents for such operations as barriers, multicast, and reductions. The reconfigurable tree apparatus enables an agent to initiate a... Agent:

20150006850 - Processor with heterogeneous clustered architecture: Provided is a processor with a heterogeneous clustered architecture. The processor comprises a first cluster comprising a first functional unit configured to process a first type of instruction, and a register whose I/O ports are connected to I/O ports of the functional unit; and a second cluster comprising a second... Agent: Samsung Electronics Co., Ltd

20150006853 - Apparatus and method to accelerate compression and decompression operations: A processor is described that includes an instruction execution pipeline having an instruction fetch unit to fetch and decode an instruction. The processor also has an execution unit to execute the instruction. The execution unit has a state machine and content addressable memory (CAM) circuitry. The state machine is to... Agent:

20150006852 - Forming instruction groups based on decode time instruction optimization: Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be included in a current instruction group or another instruction group. This determination is made based on whether the instruction is... Agent:

20150006851 - Instruction order enforcement pairs of instructions, processors, methods, and systems: A processor of an aspect includes an instruction fetch unit to fetch a pair of instruction order enforcement instructions. The pair of instruction order enforcement instructions are part of an instruction set of the processor. The pair of instruction order enforcement instructions includes an activation instruction and an enforcement instruction.... Agent:

20150006855 - Predictive fetching and decoding for selected instructions: Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based... Agent:

20150006854 - Predictive fetching and decoding for selected return instructions: Predictive fetching and decoding for selected instructions. A determination is made as to whether an instruction to be executed in a pipelined processor is a selected return instruction, the pipelined processor having a plurality of stages including an execute stage. Based on the instruction being the selected return instruction, obtaining... Agent:

20150006856 - Mode dependent partial width load to wider register processors, methods, and systems: A method of an aspect is performed by a processor. The method includes receiving a partial width load instruction. The partial width load instruction indicates a memory location of a memory as a source operand and indicates a register as a destination operand. The method includes loading data from the... Agent:

20150006858 - Packed data element predication processors, methods, systems, and instructions: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first... Agent:

20150006857 - Processors, methods, systems, and instructions to transcode variable length code points of unicode characters: A processor includes a plurality of packed data registers. The processor also includes a decode unit to decode a packed variable length code point length determination instruction. The instruction is to indicate a first source packed data that is to have a plurality of packed variable length code points that... Agent:

20150006859 - Multifunctional hexadecimal instruction form system and program product: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point... Agent:

20150006860 - Rotate then operate on selected bits facility and instructions therefor: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register.... Agent:

20150006861 - Common architecture state presentation for processor having processing cores of different types: A method is described that includes deciding to migrate a thread from a first processing core to a second processing core. The method also includes automatically in hardware migrating first context of the thread of the first processing core whose register definition is also found on the second processing core... Agent:

20150006862 - Predictor data structure for use in pipelined processing: A predictor data structure is used for pipelined processing by a pipelined processor. The predictor data structure includes a predicted address to be used in return from execution of a selected instruction, and a predicted operating state associated with the predicted address. Based on determining a selected return instruction is... Agent:

20150006863 - Debug method and device for providing indexed trace messages: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a... Agent: Freescale Semiconductor, Inc.

20150006864 - Register window performance via lazy register fills: The present embodiments provide a system that facilitates lazy register window fills in a processor. During program execution, when the system encounters a restore instruction for a register window, the system determines if the restore instruction causes an underflow condition that requires the register window to be filled from a... Agent:

20150006866 - Optimization of instruction groups across group boundaries: Instructions grouped into instruction groups are optimized across group boundaries. Instruction sequences spanning multiple groups are optimized by retaining information relating to an instruction at the end of one instruction group to be co-optimized with an instruction at the beginning of a subsequent instruction group. This retained information is then... Agent:

20150006867 - Optimization of instruction groups across group boundaries: Instructions grouped into instruction groups are optimized across group boundaries. Instruction sequences spanning multiple groups are optimized by retaining information relating to an instruction at the end of one instruction group to be co-optimized with an instruction at the beginning of a subsequent instruction group. This retained information is then... Agent: International Business Machines Corporation

20150006865 - Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register: A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different... Agent:

20150006868 - Minimizing bandwith to compress output stream in instruction tracing systems: In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method... Agent:

20150006869 - Debug method and device for handling exceptions and interrupts: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a... Agent: Freescale Semiconductor, Inc.

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