Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions

20090271591 - Vector simd processor: A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction... Agent: Miles & Stockbridge PC

20090271592 - Apparatus for storing instructions in a multithreading microprocessor: A circuit for selecting one of N requesters in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090271593 - Patching device for patching rom code, method for patching rom code, and electronic device utilizing the same: An electronic device comprising a ROM, a reprogrammable memory, a processor, and a patching device. The ROM stores a first function starting from a first address, the reprogrammable memory stores a second function starting from a second address, the patching device couples to the ROM and the reprogrammable memory, and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090271594 - Semiconductor integrated circuit, semiconductor integrated circuit control device, load distribution method, load distribution program, and electronic device: A damage control unit includes: a switching judgment unit to judge the CPU configuration which performs smoothing of the damage ratio, according to the damage ratio of the CPUs; and a switching unit to perform switching of I/O signals of all the CPUs. The switching judgment unit observes the damage... Agent: Nec Corporation Of America

20090271595 - Configuring an application for execution on a parallel computer: Methods, systems, and products are disclosed for configuring an application for execution on a parallel computer that include: booting up a first subset of a plurality of nodes in a serial processing mode; booting up a second subset of the plurality of nodes in a parallel processing mode; profiling, prior... Agent: Ibm (roc-blf)

20090271596 - Executing an application on a parallel computer: Methods, systems, and products are disclosed for executing an application on a parallel computer having a plurality of nodes. Executing an application on a parallel computer includes: booting up a first subset of a plurality of nodes in a serial processing mode; booting up a second subset of the plurality... Agent: Ibm (roc-blf)

20090271597 - Branch prediction in a computer processor: Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most... Agent: Ibm (roc-blf)

20090265527 - Multiport execution target delay queue fifo array: One embodiment provides a method of forwarding data in a processor. The method generally includes providing at least one cascaded delayed execution pipeline unit having at least a first pipeline and a second pipeline for executing first and second instructions in a common issue group, wherein the second pipeline executes... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090265528 - Programmable streaming processor with mixed precision instruction execution: The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and... Agent: Qualcomm Incorporated

20090265529 - Processor apparatus and method of processing multiple data by single instructions: A processor (and method) of processing multiple data by a single instruction includes first and second register sets each of which includes a plurality of registers, and an arithmetic unit to rearrange data being registered in the first and second register sets according to a relative size of an absolute... Agent: Mcginn Intellectual Property Law Group, PLLC

20090265531 - Code evaluation for in-order processing: Systems and methods of code evaluation for in-order processing are disclosed. In an embodiment, the method includes identifying a first instruction having multiple execution source paths. The method also includes generating a first execution path model identifying an execution order of multiple instructions based on a first condition and generating... Agent: Qualcomm Incorporated

20090265530 - Latency hiding of traces using block coloring: An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information. The blocks correspond to a program trace and containing a wait instruction. The wait instruction is sunk down the... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090265532 - Anti-prefetch instruction: Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090265533 - Branch prediction mechanisms using multiple hash functions: In one embodiment, the branch prediction mechanism includes a first storage including a first plurality of locations for storing a first set of partial prediction information. The branch prediction mechanism also includes a second storage including a second plurality of locations for storing a second set of partial prediction information.... Agent: Mhkkg/sun

20090265534 - Fairness, performance, and livelock assessment using a loop manager with comparative parallel looping: A method, apparatus, and computer program are provided for assessing fairness, performance, and livelock in a logic development process utilizing comparative parallel looping. Multiple loop macros are generated, the multiple loop macros respectively correspond to multiple processor threads, and the multiple loop macros are parallel comparative loop macros. The multiple... Agent: Cantor Colburn LLP - IBM Rochester Division

20090259823 - Circuit and design structure for a streaming digital data filter: A circuit and design structure for a streaming digital data filter embodied in a machine readable medium, the design structure including: a data processing unit and a pointer processing unit, the data processing unit and the pointer unit connected to a control logic; the pointer processing unit consisting of n... Agent: Schmeiser, Olsen & Watts

20090259822 - Streaming digital data filter: A method of filtering streaming digital data in real time. The method including: (a) initializing and storing a set of m data elements and an associated set of m pointer data from 1 to m in sequence, m an integer greater than 2; (b) receiving in real time a first... Agent: Schmeiser, Olsen & Watts

20090259824 - Reconfigurable integrated circuit: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated... Agent: Dennison, Schultz & Macdonald

20090259825 - Multi-core processing system: A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet... Agent: Freescale Semiconductor, Inc. Law Department

20090259826 - Microprocessor extended instruction set mode: Disclosed is a system and method of adding functionality to a microprocessor, especially a RISC machine having a plurality of cores, with minimal changes in circuitry and while maintaining legacy features. An enhancement to the microprocessor involves modifying a program counter register (P-register). This invention increases the number of bits... Agent: Henneman & Associates, PLC

20090259827 - System, method, and computer program product for creating dependencies amongst instructions using tags: A system, method, and computer program product are provided for creating dependencies amongst instructions using tags. In operation, tags are associated with a first instruction and a second instruction. Additionally, a dependency is created between the first instruction and the second instruction, utilizing the tags. Furthermore, the first instruction and... Agent: Zilka-kotab, PC- Rmi

20090259828 - Execution of retargetted graphics processor accelerated code by a general purpose processor: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core... Agent: Patterson & Sheridan, L.L.P.

20090259829 - Thread-local memory reference promotion for translating cuda code for execution by a general purpose processor: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core... Agent: Patterson & Sheridan, L.L.P.

20090259831 - Defining memory indifferent trace handles: A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace.... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090259830 - Quantifying completion stalls using instruction sampling: A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath,... Agent: Ibm Corp. (mrn) C/o Law Office Of Michael R. Nichols

20090259832 - Retargetting an application program for execution by a general purpose processor: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core... Agent: Patterson & Sheridan, L.L.P.

20090254734 - Partial load/store forward prediction: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality... Agent: Mhkkg, PC/apple, Inc.

20090254735 - Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture: A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstruction that specifies an N-bit first source register, an 8-bit second source register, and... Agent: Huffman Law Group, P.C.

20090254736 - Data processing system for performing data rearrangement operations: An apparatus for processing data is provided comprising rearrangement circuitry having a plurality of rearrangement stages for rearranging a plurality N of input data elements, each rearrangement stage comprising at most N multiplexers arranged to select between M data elements where M is in integer less than N. Control circuitry... Agent: Nixon & Vanderhye, PC

20090254737 - Information processing device, information processing supporting server and information processing system: In information processing device or the like is provided to output a suitable form of information from a view point of user's non-feeling of trouble. In the information processing system, whether a user issues an output instruction or not is confirmed only with respect to information that is not extracted... Agent: Lahive & Cockfield, LLP Floor 30, Suite 3000

20090254738 - Obfuscation device, processing device, method, program, and integrated circuit thereof: It is an object of the present invention to provide an obfuscation device that can achieve both sufficient obfuscation and the appropriate instruction block to be executed. In the obfuscation device, a first instruction generating unit, for each of the first process and the second process, generates an initialization instruction... Agent: Wenderoth, Lind & Ponack L.L.P.

20090254739 - Information processing device: An information processing device having a function for efficiently debugging a parallel processing program by controlling snoop operation is provided. The information processing device is so configured that the following is implemented: the setting for receiving a snoop request from a central processing unit can be set at a snoop... Agent: Miles & Stockbridge PC

20090254740 - Information processing device, encryption method of instruction code, and decryption method of encrypted instruction code: It is possible to achieve the protection of software with reduced overhead. For example, a memory for storing an encrypted code prepared in advance and a decryptor module for decrypting the code are provided. The decryptor module includes, for example, a three-stage pipeline and a selector for selecting one output... Agent: Miles & Stockbridge PC