Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
10/02/2014 > 7 patent applications in 6 patent subcategories.

20140297992 - Apparatus and method for generating vector code: An apparatus and method for generating vector code are provided. The apparatus and method generate vector code using scalar-type kernel code, without user's changing a code type or modifying data layout, thereby enhancing user's convenience of use and retaining the portability of OpenCL.... Agent: Samsung Electronics Co., Ltd.

20140297991 - Instructions for storing in general purpose registers one of two scalar constants based on the contents of vector write masks: According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single... Agent:

20140297993 - Uncore microcode rom: A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of... Agent: Via Technologies, Inc.

20140297994 - Processors, methods, and systems to implement partial register accesses with masked full register accesses: A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand,... Agent:

20140297995 - Fault-tolerant system and fault-tolerant operating method: A fault-tolerant system including a calculation unit and an output synthesizer is provided. The calculation unit receives a first environmental parameter and input data, wherein the calculation unit further includes a first and a second calculation circuits. The first calculation circuit is arranged to perform a calculation on the input... Agent: Industrial Technology Research Institute

20140297996 - Multiple hash table indexing: A processor includes storage elements to store a first and second value, as well as a plurality of hash units coupled to the storage elements. Each hash unit performs a hash operation using the first value and the second value to generate a corresponding hash result value. The processor further... Agent: Advanced Micro Devices, Inc.

20140297997 - Automated cooperative concurrency with minimal syntax: Various embodiments are generally directed to techniques for reducing syntax requirements in application code to cause concurrent execution of multiple iterations of at least a portion of a loop thereof to reduce overall execution time in solving a large scale problem. At least one non-transitory machine-readable storage medium includes instructions... Agent: Sas Institute Inc.

  
09/25/2014 > 10 patent applications in 8 patent subcategories.

20140289494 - Instruction and logic to provide vector horizontal majority voting functionality: Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values... Agent: Intel Corporation

20140289495 - Enhanced predicate registers: Systems, apparatuses and methods for utilizing enhanced predicate registers which specify the element width and which elements are to be processed. The predicate size is dynamic, depending on the contents of the enhanced predicate register used for an instruction rather than being a static quality of a specific instruction. Specifying... Agent: Apple Inc.

20140289497 - Enhanced macroscalar comparison operations: Systems, apparatuses and methods for utilizing enhanced Macroscalar comparison operations which take an enhanced predicate operand that designates the element width and which elements are to be processed. The element width and the number of elements per vector are determined at run-time rather than being defined in the architectural definition... Agent: Apple Inc.

20140289496 - Enhanced macroscalar predicate operations: Systems, apparatuses and methods for utilizing enhanced macroscalar predicate operations which take enhanced predicate operands that designate the element width and which elements are to be processed. The element width and the number of elements per vector are determined at run-time rather than being defined in the architectural definition of... Agent: Apple Inc.

20140289498 - Enhanced macroscalar vector operations: Systems, apparatuses and methods for utilizing enhanced Macroscalar vector operations which take an enhanced predicate operand that designates the element width and which elements are to be processed. The element width and the number of elements per vector are determined at run-time rather than being defined in the architectural definition... Agent: Apple Inc.

20140289499 - Switching between dedicated function hardware and use of a software routine to generate result data: An apparatus for processing data 2 is provided including processing circuitry 24 controlled by an instruction decoder 20 in response to a stream of program instructions. There is also provided dedicated function hardware 12 configured to receive output data from the processing circuitry and to perform a dedicated processing operation.... Agent:

20140289500 - Method and apparatus for providing an interface between a uicc and a processor in an access terminal that supports asynchronous command processing by the uicc: Techniques for providing an interface between a UICC and a processor, included in an access terminal, that supports asynchronous command processing by the UICC, are described. A first complex command, with a first processing time, may be received from the processor. An initial response to the first command, including a... Agent: Qualcomm Incorporated

20140289501 - Technique for freeing renamed registers: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured... Agent:

20140289502 - Enhanced vector true/false predicate-generating instructions: Systems, apparatuses and methods for utilizing enhanced vector true/false instructions. The enhanced vector true/false instructions generate enhanced predicates to correspond to the request element width and/or vector size. A vector true instruction generates an enhanced predicate where all elements supported by the processing unit are active. A vector false instruction... Agent: Apple Inc.

20140289503 - Packed data operation mask comparison processors, methods, systems, and instructions: Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit... Agent:

  
09/18/2014 > 75 patent applications in 31 patent subcategories.

20140281369 - Apparatus and method for sliding window data gather: An apparatus and method are described for fetching and storing a plurality of portions of a data stream into a plurality of registers. For example, a method according to one embodiment includes the following operations: determining a set of N vector registers into which to read N designated portions of... Agent:

20140281368 - Cycle sliced vectors and slot execution on a shared datapath: An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example... Agent: Qualcomm Incorporated

20140281373 - Digital signal processor and baseband communication device: A digital signal processor has a vector execution unit arranged to execute instructions on multiple data in the form of a vector, comprising a local queue arranged to receive instructions from a program memory and to hold them in the local queue until a predefined condition is fulfilled. The local... Agent: Mediatek Sweden Ab

20140281371 - Techniques for enabling bit-parallel wide string matching with a simd register: Various embodiments are generally directed to overcoming limitations of vector registers in their use with bit-parallel string matching algorithms. An apparatus includes a processor element; and logic to receive a pattern comprising a first string of elements to employ in a string matching operation, instantiate a test bitmask in a... Agent:

20140281372 - Vector indirect element vertical addressing mode with horizontal permute: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements,... Agent: Qualcomm Incorporated

20140281370 - Vector processing engines having programmable data path configurations for providing multi-mode vector processing, and related vector processors, systems, and methods: Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs include a vector processing stage(s) configured to process vector data according to a vector instruction executed in the vector processing stage.... Agent: Qualcomm Incorporated

20140281374 - Identifying logical planes formed of compute nodes of a subcommunicator in a parallel computer: In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the subcommunicator and for a number of dimensions beginning with a first dimension: establishing, by a plane building node, in a positive direction of the... Agent: International Business Machines Corporation

20140281375 - Run-time instrumentation handling in a superscalar processor: A method and a computer program for a processor simultaneously handle multiple instructions at a time. The method includes labeling of an instruction ending a relevant sample interval from a plurality of such instructions. Further, the method utilizes a buffer to store N more number of entries than actually required,... Agent: International Business Machines Corporation

20140281376 - Creating an isolated execution environment in a co-designed processor: In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and... Agent:

20140281379 - Hybrid programmable many-core device with on-chip interconnect: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may... Agent: Altera Corporation

20140281377 - Identifying logical planes formed of compute nodes of a subcommunicator in a parallel computer: In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the subcommunicator and for a number of dimensions beginning with a first dimension: establishing, by a plane building node, in a positive direction of the... Agent: International Business Machines Corporation

20140281378 - Three-dimensional computer processor systems having multiple local power and cooling layers and a global interconnection structure: A computer processor system includes a plurality of multi-chip systems that are physically aggregated and conjoined. Each multi-chip system includes a plurality of chips that are conjoined together, and a local interconnection and input/output wiring layer. A global interconnection network is connected to the local interconnection and input/output wiring layer... Agent: International Business Machines Corporation

20140281380 - Execution context swap between heterogenous functional hardware units: Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts... Agent:

20140281381 - System-on-chip and method of operating the same: A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to... Agent: Samsung Electronics Co., Ltd.

20140281383 - Ground-referenced single-ended signaling connected graphics processing unit multi-chip module: A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit.... Agent: Nvidia Corporation

20140281384 - Method and apparatus for predicting forwarding of data from a store to a load: A method for gating a load operation based on entries of a prediction table is presented. The method comprises performing a look-up for the load operation in a prediction table to find a matching entry, wherein the matching entry corresponds to a prediction regarding a behavior of the load operation,... Agent: Soft Machines, Inc.

20140281382 - Modified execution using context sensitive auxiliary code: A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded... Agent: Intel Corporation

20140281385 - Configurable multicore network processor: A network processor includes a plurality of processing cores configured to process data packets, and a processing mode mechanism configurable to configure the processing cores between a pipeline processing mode and a parallel processing mode. The processing mode mechanism may include switch elements, or a fabric logic and a bus,... Agent: Qualcomm Incorporated

20140281386 - Chaining between exposed vector pipelines: Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at... Agent: International Business Machines Corporation

20140281387 - Converting conditional short forward branches to computationally equivalent predicated instructions: A processor is operable to process conditional branches. The processor includes instruction fetch logic to fetch a conditional short forward branch. The conditional short forward branch is to include a conditional branch instruction and a set of one or more instructions that are to sequentially follow the conditional branch instruction... Agent:

20140281388 - Method and apparatus for guest return address stack emulation supporting speculation: A microprocessor implemented method for maintaining a guest return address stack in an out-of-order microprocessor pipeline is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each function call instruction in the native... Agent: Soft Machines, Inc.

20140281389 - Methods and apparatus for fusing instructions to provide or-test and and-test functionality on multiple test sources: Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition.... Agent:

20140281390 - System and method for ordering packet transfers in a data processor: A data processor includes a packet selector. The packet selector creates an ordered list of packets, each packet corresponding to a respective communication flow, determines whether each packet in the ordered list of packets is eligible for transfer to a prefetch unit based on whether a preceding packet in the... Agent: Freescale Semiconductor, Inc.

20140281397 - Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources: Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform... Agent:

20140281398 - Instruction emulation processors, methods, and systems: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to... Agent:

20140281391 - Method and apparatus for forwarding literal generated data to dependent instructions more efficiently using a constant cache: A processor to a store constant value (immediate or literal) in a cache upon decoding a move immediate instruction in which the immediate is to be moved (copied or written) to an architected register. The constant value is stored in an entry in the cache. Each entry in the cache... Agent: Qualcomm Incorporated

20140281394 - Method to improve speed of executing return branch instructions in a processor: An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a... Agent: Qualcomm Incorporated

20140281396 - Processors, methods, systems, and instructions to consolidate unmasked elements of operation masks: An instruction processing apparatus of an aspect includes a plurality of operation mask registers. The apparatus also includes a decode unit to receive an operation mask consolidation instruction. The operation mask consolidation instruction is to indicate a source operation mask register, of the plurality of operation mask registers, and a... Agent:

20140281392 - Profiling code portions to generate translations: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions... Agent: Nvidia Corporation

20140281393 - Reorder-buffer-based static checkpointing for rename table rebuilding: Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a... Agent:

20140281395 - Systems, apparatuses, and methods for reducing the number of short integer multiplications: Systems, methods, and apparatuses for calculating a square of a data value of a first source operand, a square of a data value of a second source operand, and a multiplication of the data of the first and second operands only using one multiplication are described.... Agent:

20140281399 - Instruction emulation processors, methods, and systems: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to... Agent:

20140281401 - Systems, apparatuses, and methods for determining a trailing least significant masking bit of a writemask register: The execution of a KZBTZ finds a trailing least significant zero bit position in an first input mask and sets an output mask to have the values of the first input mask, but with all bit positions closer to the most significant bit position than the trailing least significant zero... Agent:

20140281400 - Systems, apparatuses,and methods for zeroing of bits in a data element: Embodiments of systems, methods and apparatuses for execution a NAME instruction are described. The execution of a VPBZHI causes, on a per data element basis of a second source, a zeroing of bits higher (more significant) than a starting point in the data element. The starting point is defined by... Agent:

20140281403 - Chaining between exposed vector pipelines: Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at... Agent: International Business Machines Corporation

20140281402 - Processor with hybrid pipeline capable of operating in out-of-order and in-order modes: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may... Agent: International Business Machines Corporation

20140281406 - Instruction for performing an overload check: A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.... Agent:

20140281409 - Method and apparatus for nearest potential store tagging: A method for performing memory disambiguation in an out-of-order microprocessor pipeline is disclosed. The method comprises storing a tag with a load operation, wherein the tag is an identification number representing a store instruction nearest to the load operation, wherein the store instruction is older with respect to the load... Agent: Soft Machines, Inc.

20140281408 - Method and apparatus for predicting forwarding of data from a store to a load: A method for gating a load operation based on entries of a prediction table is presented. The method comprises performing a look-up for the load operation in a prediction table to find a matching entry, wherein the matching entry corresponds to a prediction regarding a behavior of the load operation,... Agent: Soft Machines, Inc.

20140281410 - Method and apparatus to allow early dependency resolution and data forwarding in a microprocessor: A microprocessor implemented method for performing early dependency resolution and data forwarding is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each current guest branch instruction in the native address space fetched... Agent: Soft Machines, Inc.

20140281411 - Method for dependency broadcasting through a source organized source view data structure: A method for dependency broadcasting through a source organized source view data structure. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register... Agent: Soft Machines, Inc.

20140281412 - Method for populating and instruction view data structure by using register template snapshots: A method for populating an instruction view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the... Agent: Soft Machines, Inc.

20140281407 - Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture: Methods, apparatus, systems, and articles of manufacture to compile instructions for a vector of instruction pointers (VIP) processor architecture are disclosed. An example method includes identifying a predicate dependency between a first compiled instruction and a second compiled instruction at a control flow join point, the second compiled instruction having... Agent:

20140281405 - Optimizing performance for context-dependent instructions: A processor includes a queue for storing instructions processed within the context of a current value of a register field, where for some embodiments the instruction is undefined or defined, depending upon the register field at time of processing. After a write instruction (an instruction that writes to the register... Agent:

20140281404 - System and method to clear and rebuild dependencies: A data processing system and method of clearing and rebuilding dependencies, the data processing method including changing a counter associated with a first entry in response to selecting a second entry; comparing the counter with a threshold; and indicating that the first entry is ready to be selected in response... Agent:

20140281415 - Dynamic rename based register reconfiguration of a vector register file: Reconfiguring a register file using a rename table having a plurality of fields that indicate fracture information about a source register of an instruction for instructions which have narrow to wide dependencies.... Agent:

20140281414 - Reorder-buffer-based dynamic checkpointing for rename table rebuilding: Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a... Agent:

20140281413 - Superforwarding processor: Methods and systems that allow the processor to effectively and efficiently reduce or eliminate the latency associated with instructions that copy the value of one register to another register. A processor includes a superforwarding table, a superforwarding logic block, and a computation engine. The superforwarding table stores an entry, wherein... Agent: Mips Technologies, Inc.

20140281416 - Method for implementing a reduced size register view data structure in a microprocessor: A method for implementing a reduced size register view data structure in a microprocessor. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of multiplexers to access ports of a scheduling array to store the instruction... Agent: Soft Machines, Inc.

20140281418 - Multiple data element-to-multiple data element comparison processors, methods, systems, and instructions: An apparatus includes packed data registers and an execution unit. An instruction is to indicate a first source packed data that is to include a first packed data elements, a second source packed data that is to include a second packed data elements, and a destination storage location. The execution... Agent:

20140281417 - Systems, methods, and computer program products providing a data unit sequencing queue: A system for passing data, the system including multiple data producers passing processed data, wherein the processed data include discrete data units that are each consecutively numbered, each of the data producers calculating insertion indices for ones of the data units passing therethrough; a circular buffer receiving the data units... Agent: Genband US LLC

20140281420 - Add-compare-select instruction: An apparatus includes memory storing an instruction that identifies a first register, a second register, and a third register. Upon execution of the instruction by a processor, a vector addition operation is performed by the processor to add first values from the first register to second values from the second... Agent: Qualcomm Incorporated

20140281421 - Arbitrary size table lookup and permutes with crossbar: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in... Agent: Qualcomm Incorporated

20140281419 - Combined floating point multiplier adder with intermediate rounding logic: An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated... Agent: Intel Corporation

20140281422 - Method and apparatus for sorting elements in hardware structures: A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits... Agent: Soft Machines, Inc.

20140281425 - Limited range vector memory access instructions, processors, methods, and systems: A processor of an aspect includes a plurality of packed data registers. The processor also includes a unit coupled with the packed data registers. The unit is operable, in response to a limited range vector memory access instruction. The instruction is to indicate a source packed memory indices, which is... Agent:

20140281427 - Method for implementing a reduced size register view data structure in a microprocessor: A method for implementing a reduced size register view data structure in a microprocessor. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the... Agent: Soft Machines, Inc.

20140281426 - Method for populating a source view data structure by using register template snapshots: A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the... Agent: Soft Machines, Inc.

20140281428 - Method for populating register view data structure by using register template snapshots: A method for populating a register view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the... Agent: Soft Machines, Inc.

20140281423 - Processor and method for processing instructions using at least one processing pipeline: A processor has a processing pipeline with first, second and third stages. An instruction at the first stage takes fewer cycles to reach the second stage then the third stage. The second and third stages each have a duplicated processing resource. For a pending instruction which requires the duplicated resource... Agent:

20140281424 - Tracking control flow of instructions: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in... Agent:

20140281431 - Efficient way to cancel speculative 'source ready' in scheduler for direct and nested dependent instructions: A method and apparatus for simultaneously canceling a dependent instruction and a nested dependent instruction when a cancel timer of a source of the dependent instruction and a cancel timer of a source of the nested dependent instruction expire and a producer instruction speculatively waking up the dependent instruction is... Agent:

20140281429 - Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable media: Embodiments disclosed herein include eliminating redundant synchronization barriers from execution pipelines in instruction processing circuits. Related processor systems, methods, and computer-readable media are also disclosed. By tracking the occurrence of synchronization events, unnecessary software synchronization operations may be identified and eliminated, thus improving performance of a central processing unit (CPU).... Agent: Qualcomm Incorporated

20140281430 - Execution of condition-based instructions: Execution of condition-based instructions is facilitated. A condition-based instruction is obtained, as well as a confidence level associated with the instruction. The confidence level is checked, and based on the confidence level being a first value, a predicted operation of the instruction, which is based on a predictor, is unconditionally... Agent: International Business Machines Corporation

20140281432 - Systems and methods for move elimination with bypass multiple instantiation table: Systems and methods for move operation elimination with bypass Multiple Instantiation Table (MIT) logic. An example processing system may comprise a first data structure configured to store a plurality of physical register values; a second data structure configured to store a plurality of pointers, each pointer referencing an element of... Agent:

20140281433 - Apparatus and method for tracing exceptions: A data processing apparatus comprises processing circuitry for executing a stream of instructions, and exception handling circuitry for selecting, from one or more exceptions, an exception to be handled by the processing circuitry. The unselected exceptions are referred to as pending exceptions. The data processing apparatus further comprises trace generating... Agent:

20140281436 - Method for emulating a guest centralized flag architecture by using a native distributed flag architecture: A method for emulating a guest centralized flag architecture by using a native distributed flag architecture. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of... Agent: Soft Machines, Inc.

20140281435 - Method to paralleize loops in the presence of possible memory aliases: In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that... Agent: Analog Devices Technology

20140281434 - Path profiling using hardware and software combination: A mechanism for generating a path profile is disclosed. A profiling module may insert profiling instructions into instruction blocks. The profiling instructions may generate a path identifier as a processor executes an execution path executes a sequence or path of instruction blocks). A path identifier module may add path identifiers... Agent:

20140281437 - Robust and high performance instructions for system call: Robust system call and system return instructions are executed by a processor to transfer control between a requester and an operating system kernel. The processor includes execution circuitry and registers that store pointers to data structures in memory. The execution circuitry receives a system call instruction from a requester to... Agent:

20140281438 - Method for a delayed branch implementation by using a front end track table: A method for a delayed branch implementation by using a front end track table. The method includes receiving an incoming instruction sequence using a global front end, wherein the instruction sequence includes at least one branch, creating a delayed branch in response to receiving the one branch, and using a... Agent: Soft Machines, Inc.

20140281439 - Hardware optimization of hard-to-predict short forward branches: Methods and apparatuses for optimizing hard-to-predict short forward branches. A method detects a forward conditional branch with at least one instruction between the forward conditional branch and forward conditional branch target. The method determines whether a first of the at least one instruction includes at least one of a conditional... Agent: Qualcomm Incorporated

20140281441 - Indirect branch prediction: Methods and indirect branch predictor logic units to predict the target addresses of indirect branch instructions. The method comprises storing in a table predicted target addresses for indirect branch instructions indexed by a combination of the indirect path history for previous indirect branch instructions and the taken/not-taken history for previous... Agent: Imagination Technologies, Ltd.

20140281440 - Precalculating the direct branch partial target address during missprediction correction process: An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also... Agent: Qualcomm Incorporated

20140281442 - System management and instruction counting: Techniques for managing a plurality of threads on a multi-threading processing core. Embodiments provide an instruction count threshold condition that determines how many countable instructions of a thread the multi-threading processing core will execute before context switching to another one of the plurality of threads. A first plurality of instructions... Agent: International Business Machines Corporation

  
09/11/2014 > 42 patent applications in 16 patent subcategories.

20140258677 - Analyzing potential benefits of vectorization: Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for analyzing execution of a plurality of executable instructions and, based on the analysis, providing an indication of a benefit to be obtained by vectorization of at least a subset of the plurality of... Agent:

20140258678 - Parallel configuration of a reconfigurable instruction cell array: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch... Agent: Qualcomm Incorporated

20140258679 - Reconfigurable protocol tables within an asic: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions... Agent: Silicon Graphics International Corp.

20140258680 - Parallel dispatch of coprocessor instructions in a multi-thread processor: Techniques are addressed for parallel dispatch of coprocessor and thread instructions to a coprocessor coupled to a threaded processor. A first packet of threaded processor instructions is accessed from an instruction fetch queue (IFQ) and a second packet of coprocessor instructions is accessed from the IFQ. The IFQ includes a... Agent: Qualcomm Incorporated

20140258681 - Anticipated prefetching for a parent core in a multi-core chip: Embodiments relate to prefetching data on a chip having a scout core and a parent core coupled to the scout core. The method includes determining that a program executed by the parent core requires content stored in a location remote from the parent core. The method includes sending a fetch... Agent: International Business Machines Corporation

20140258682 - Pipelined processor: Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which... Agent: Advanced Digital Chips Inc.

20140258683 - Instruction and logic to provide vector horizontal compare functionality: Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of... Agent: Intel Corporation

20140258686 - Integrated circuit, electronic device and instruction scheduling method: An integrated circuit comprising a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies is disclosed. The integrated circuit further includes an instruction scheduler adapted to evaluate data dependencies between individual instructions in a received plurality... Agent: Nxp B.v.

20140258684 - System and method to increase lockstep core availability: A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or... Agent: Infineon Technologies Ag

20140258685 - Using reduced instruction set cores: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be... Agent:

20140258687 - Micro-ops including packed source and destination fields: A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a... Agent:

20140258688 - Benchmark generation using instruction execution information: Methods and systems are provided for generating a benchmark representative of a reference process. One method involves obtaining execution information for a subset of the plurality of instructions of the reference process from a pipeline of a processing module during execution of those instructions by the processing module, determining performance... Agent: Advanced Micro Devices, Inc.

20140258689 - Processor for large graph algorithm computations and matrix operations: A node processor and method for performing matrix operations includes storing, in memory, non-zero matrix elements of a first sparse matrix, non-zero matrix elements of a second sparse matrix, and matrix elements of a sparse results matrix mapped to the node processor. A matrix communications module exchanges with other node... Agent: Massachusetts Institute Of Technology

20140258690 - Apparatus and method for non-blocking execution of static scheduled processor: An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one... Agent: Samsung Electronics Co., Ltd.

20140258691 - Thread transition management: Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on... Agent: International Business Machines Corporation

20140258692 - Data processor: A RISC data processor in which the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. An instruction for generating flags according to operands' data sizes is defined, and... Agent: Renesas Electronics Corporation

20140258693 - System and method for hardware scheduling of conditional barriers and impatient barriers: A method and a system are provided for hardware scheduling of barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated, and when each thread reaches the barrier instruction during execution of program, it is determined whether the thread... Agent: Nvidia Corporation

20140258694 - Apparatus and method for branch instruction bonding: A processor is configured to identify a branch instruction immediately followed by an architectural delay slot. A single bonded instruction comprising the branch instruction immediately followed by the architectural delay slot is created. The single bonded instruction is loaded into an instruction buffer.... Agent: Mips Technologies, Inc.

20140258695 - Last branch record indicators for transactional memory: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction.... Agent:

20140258696 - Strided target address predictor (stap) for indirect branches: Systems and methods for predicting an indirect branch target address. A strided target address predictor (STAP) system can observe a striding pattern from a previous indirect branch target. The system can predict a target address based on the observed striding pattern. The system can initialize a confidence counter. The system... Agent: Qualcomm Incorporated

20140258697 - Apparatus and method for transitive instruction scheduling: A processor includes a multiple stage pipeline with a scheduler with a wakeup block and select logic. The wakeup block is configured to wake, in a first cycle, all instructions dependent upon a first selected instruction to form a wake instruction set. In a second cycle, the wakeup block wakes... Agent: Mips Technologies, Inc.

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