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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
04/16/2015 > 16 patent applications in 11 patent subcategories.

20150106589 - Small form high performance computing mini hpc: A computing platform comprising a small form factor high performance computer for mobile high performance computing is provided. The computing platform comprises using small form factor design with a 64-core microprocessor/co-processor is provided. The small form factor high performance computer may include 64-core microprocessor/co-processors based on the ANNI Stem Cell... Agent:

20150106590 - Filtering out redundant software prefetch instructions: The disclosed embodiments relate to a system that selectively filters out redundant software prefetch instructions during execution of a program on a processor. During execution of the program, the system collects information associated with hit rates for individual software prefetch instructions as the individual software prefetch instructions are executed, wherein... Agent: Oracle International Corporation

20150106591 - Instruction and logic for processing text strings: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding... Agent:

20150106592 - Instruction and logic for processing text strings: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding... Agent:

20150106593 - Instruction and logic for processing text strings: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding... Agent:

20150106594 - Instruction and logic for processing text strings: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding... Agent:

20150106595 - Prioritizing instructions based on type: Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category... Agent:

20150106596 - Data processing system having integrated pipelined array data processor: A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.... Agent: Pact Xpp Technologies Ag

20150106598 - Computer processor employing efficient bypass network for result operand routing: A computer processor is provided with a plurality of functional units that performs operations specified by the at least one instruction over the multiple machine cycles, wherein the operations produce result operands. The processor also includes circuitry that generates result tags dynamically according to the number of operations that produce... Agent: Mill Computing, Inc.

20150106597 - Computer processor with deferred operations: A computer processor and corresponding method of operation employs execution logic that includes at least one functional unit and operand storage that stores data that is produced and consumed by the at least one functional unit. The at least one functional unit is configured to execute a deferred operation whose... Agent: Mill Computing, Inc.

20150106599 - Execution of a perform frame management function instruction: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.... Agent:

20150106600 - Execution of condition-based instructions: Execution of condition-based instructions is facilitated. A condition-based instruction is obtained, as well as a confidence level associated with the instruction. The confidence level is checked, and based on the confidence level being a first value, a predicted operation of the instruction, which is based on a predictor, is unconditionally... Agent:

20150106601 - Method for automatically adapting application to suitable multicore processing mode and mobile device: The present invention provides a mobile device adopting multicore processors in which each of multiple applications are automatically configured in corresponding processing modes stored in an established table. When one of the application is operated, looking up the table to select the corresponding processing mode. The mobile device automatically switches... Agent:

20150106602 - Randomly branching using hardware watchpoints: A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. The processor allocates a memory region for the purpose of creating “random branches” in the computer code utilizing existing memory access instructions. When the processor processes a given instruction, the processor both accesses... Agent: Advanced Micro Devices, Inc.

20150106603 - Method and apparatus of instruction scheduling using software pipelining: A modulo scheduling method including calculating at least two candidate initiation intervals between adjacent iterations, searching for schedules of the instructions in parallel by using the candidate initiation intervals, and selecting a schedule determined to be valid from among the searched schedules.... Agent: Samsung Electronics Co., Ltd.

20150106604 - Randomly branching using performance counters: A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. When the processor processes a given instruction of a given instruction type, the processor updates a corresponding performance counter. When the performance counter reaches a threshold, the processor generates an interrupt and compares... Agent: Advanced Micro Devices, Inc.

  
04/09/2015 > 16 patent applications in 14 patent subcategories.

20150100754 - Data processing apparatus and method for performing speculative vector access operations: A data processing apparatus and method for performing speculative vector access operations are provided. The data processing apparatus has a reconfigurable buffer accessible to vector data access circuitry and comprising a storage array for storing up to M vectors of N vectors elements. The vector data access circuitry performs speculative... Agent:

20150100755 - Data processing apparatus and method for controlling performance of speculative vector operations: A data processing apparatus and a method of controlling performance of speculative vector operations are provided. The apparatus comprises processing circuitry for performing a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements, and speculation control circuitry for maintaining a speculation width... Agent:

20150100756 - Configurable logic integrated circuit having a multidimensional structure of configurable elements: An array processor composed of processor cells that are programmed by a controlling unit, and that are reprogrammed when a cell has finished a current data processing operation, even while other cell continue to process data with their current programming.... Agent: Pact Xpp Technologies Ag

20150100757 - Incorporating a spatial array into one or more programmable processor cores: Functional units disposed in one or more processor cores are communicatively coupled using both a shared bypass network and a switched network. The shared bypass network enables the functional units to be operated conventionally for general processing while the switched network enables specialized processing in which the functional units are... Agent: Microsoft Corporation

20150100758 - Data processor and method of lane realignment: A data processor includes a register file divided into at least a first portion and a second portion for storing data. A single instruction, multiple data (SIMD) unit is also divided into at least a first lane and a second lane. The first and second lanes of the SIMD unit... Agent: Advanced Micro Devices, Inc.

20150100759 - Pipelined finite state machine: A system and method for controlling operation of a pipeline. In one embodiment, a pipelined datapath includes a plurality of processing stages and a pipeline controller. Each of the processing stages is configured to further processing provided by a previous one of the processing stages. The pipeline controller is configured... Agent: Texas Instruments Deutschland Gmbh

20150100760 - Processor to perform a bit range isolation instruction: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value... Agent: Intel Corporation

20150100761 - System-on-chip (soc) to perform a bit range isolation instruction: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value... Agent: Intel Corporation

20150100762 - Instruction cache with way prediction: A processor includes an instruction fetch unit and an execution unit. The instruction fetch unit retrieves instructions from memory to be executed by the execution unit. The instruction fetch unit includes a branch prediction unit which is configured to predict whether a branch instruction is likely to be executed. The... Agent:

20150100763 - Decoding a complex program instruction corresponding to multiple micro-operations: A data processing apparatus 2 has processing circuitry 4 which can process multiple parallel threads of processing. A shared instruction decoder 30 decodes program instructions to generate micro-operations to be processed by the processing circuitry 4. The instructions include at least one complex instruction which has multiple micro-operations. Multiple fetch... Agent:

20150100764 - Dynamically detecting uniformity and eliminating redundant computations to reduce power consumption: One embodiment of the present invention includes techniques to decrease power consumption by reducing the number of redundant operations performed. In operation, a streamlining multiprocessor (SM) identifies uniform groups of threads that, when executed, apply the same deterministic operation to uniform sets of input operands. Within each uniform group of... Agent: Nvidia Corporation

20150100765 - Disambiguation-free out of order load store queue: In a processor, a disambiguation-free out of order load store queue method. The method includes implementing a memory resource that can be accessed by a plurality of asynchronous cores; implementing a store retirement buffer, wherein stores from a store queue have entries in the store retirement buffer in original program... Agent:

20150100766 - Reordered speculative instruction sequences with a disambiguation-free out of order load store queue: In a processor, a disambiguation-free out of order load store queue method. The method includes implementing a memory resource that can be accessed by a plurality of asynchronous cores; implementing a store retirement buffer, wherein stores from a store queue have entries in the store retirement buffer in original program... Agent:

20150100767 - Self-timed user-extension instructions for a processing device: A processor for executing configurable instructions and a method of configuring the processor are disclosed. In one embodiment, the processor includes (i) a processor core to execute preconfigured instructions and (ii) a processor core extension to execute user-defined extension instructions that are configurable instructions. The user-defined extension instructions may include... Agent:

20150100768 - Scheduling program instructions with a runner-up execution position: A single instruction multiple thread (SIMT) processor 2 includes scheduling circuitry 8 for calculating a next scheduled execution point for execution circuits 4 which execute respective threads corresponding to a common program. In addition to calculating the next scheduled execution point, the scheduling circuitry determines a runner up execution point... Agent: Arm Limited

20150100769 - Processor branch cache with secondary branches: A processor uses a prediction unit to predict subsequent instructions of a program to be executed by the processor. Many implementations or combinations of implementations may be used to predict the subsequent instruction of the program. In one embodiment, a branch cache is used to store branch information. A prediction... Agent:

  
04/02/2015 > 16 patent applications in 14 patent subcategories.

20150095614 - Apparatus and method for efficient migration of architectural state between processor cores: An apparatus and method are described for the efficient migration of architectural state between processor cores. For example, a processor according to one embodiment comprises: a first processing core having a first instruction execution pipeline including first register set for storing a first architectural state of a first thread being... Agent:

20150095615 - Instruction definition to implement load store reordering and optimization: A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions, and of said sequence of instructions, splitting store instructions into a store address instruction and a store data instruction, wherein the... Agent:

20150095616 - Data processor: The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of... Agent:

20150095617 - Using software having control transfer termination instructions with software not having control transfer termination instructions: In an embodiment, the present invention includes a processor having a decode unit, an execution unit, and a retirement unit. The decode unit is to decode control transfer instructions and the execution unit is to execute control transfer instructions. The retirement unit is to retire a first control transfer instruction,... Agent:

20150095618 - Virtual load store queue having a dynamic dispatch window with a unified structure: An out of order processor. The processor includes a virtual load store queue for allocating a plurality of loads and a plurality of stores, wherein more loads and more stores can be accommodated beyond an actual physical size of the load store queue of the processor; wherein the processor allocates... Agent:

20150095619 - Request change tracker: An example request change tracker may be used to create, modify, monitor, and report events occurring within a development and testing pipeline with respect to one or more computing applications. A request change tracker may include a pipeline event detector, a testing stage detector, a control module, and a reporting... Agent: Linkedin Corporation

20150095620 - Estimating scalability of a workload: In an embodiment, a processor includes a first logic to calculate a scalability value for a processor domain based at least in part on an active state residency, a stall duration, and a memory bandwidth of the domain, and to determine an operating frequency update for the domain based at... Agent:

20150095622 - Apparatus and method for controlling execution of processes in a parallel computing system: An apparatus includes an arbiter and a plurality of arithmetic processors, each including an arithmetic circuit and a measuring circuit. The arithmetic circuit executes an arithmetic process, and the measuring circuit measures a progress level indicating a progress of the arithmetic process executed by the arithmetic circuit. Upon receiving access... Agent: Fujitsu Limited

20150095621 - Arithmetic processing unit, and method of controlling arithmetic processing unit: An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising: a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to... Agent:

20150095624 - Vector floating point test data class immediate instruction: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand... Agent:

20150095623 - Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions: A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source... Agent:

20150095625 - Optimization of instructions to reduce memory access violations: Mechanisms for reducing memory access violations are disclosed. Sets of instructions may be identified and the identified sets of instructions may be re-translated or optimized to generate other sets of instructions. Execution of the other sets of instructions is analyzed to determine whether additional memory access violations occur. When additional... Agent:

20150095626 - Trace method and information processing apparatus: An information processing apparatus includes a rewriting unit and an execution unit. The rewriting unit rewrites a first instruction described at a trace point in a function defined in a program to a second instruction which gives instructions to execute a trace code, and stores the first instruction in a... Agent:

20150095627 - Two level re-order buffer: In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may... Agent:

20150095628 - Techniques for detecting return-oriented programming: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for... Agent:

20150095629 - Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization: A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions; reordering the instructions in accordance with processor resources for dispatch and execution; ensuring a closest earlier store in machine order for... Agent:

  
03/26/2015 > 22 patent applications in 13 patent subcategories.

20150089187 - Hazard check instructions for enhanced predicate vector operations: A hazard check instruction has operands that specify addresses of vector elements to be read by first and second vector memory operations. The hazard check instruction outputs a dependency vector identifying, for each element position of the first vector corresponding to the first vector memory operation, which element position of... Agent: Apple Inc.

20150089188 - Vector hazard check instruction with reduced source operands: In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In... Agent: Apple Inc.

20150089189 - Predicate vector pack and unpack instructions: In an embodiment, a processor may implement a vector instruction set including predicate vectors and multiple vector element sizes. The vector instruction set may include predicate vector pack and unpack instructions. Responsive to the predicate vector pack instruction, the processor may pack predicates from multiple predicate vector source registers into... Agent: Apple Inc.

20150089192 - Dynamic attribute inference: In an embodiment, a processor may be configured to dynamically infer one or more attributes of input and/or output registers of an instruction, given the attributes corresponding to at least one input registers. The inference may be made at the issue circuit/stage of the processor, for those registers that do... Agent: Apple Inc.

20150089191 - Early issue of null-predicated operations: In an embodiment, a processor includes an issue circuit configured to issue instruction operations for execution. The issue circuit may be configured to monitor the source operands of the instruction operations, and to issue instruction operations for which the source operands (including predicate operands, as appropriate) are resolved. Additionally, the... Agent: Apple Inc.

20150089190 - Predicate attribute tracker: In an embodiment, a processor includes a register attribute tracker configured to track one or more attributes corresponding to registers. The register attribute tracker may track the attributes associated with the registers when those registers are used as output registers of instructions that explicitly define the attributes and, if the... Agent: Apple Inc.

20150089194 - Predictive fetching and decoding for selected instructions: Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based... Agent:

20150089193 - Predictive fetching and decoding for selected return instructions: Predictive fetching and decoding for selected instructions. A determination is made as to whether an instruction to be executed in a pipelined processor is a selected return instruction, the pipelined processor having a plurality of stages including an execute stage. Based on the instruction being the selected return instruction, obtaining... Agent:

20150089195 - Method and apparatus for performing a shift and exclusive or operation in a single instruction: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.... Agent:

20150089196 - Method and apparatus for performing a shift and exclusive or operation in a single instruction: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.... Agent:

20150089197 - Method and apparatus for performing a shift and exclusive or operation in a single instruction: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.... Agent:

20150089198 - Technique for reducing voltage droop by throttling instruction issue rate: An issue control unit is configured to control the rate at which an instruction issue unit issues instructions to an execution pipeline in order to avoid spikes in power drawn by that execution pipeline. The issue control unit maintains a history buffer that reflects, for N previous cycles, the number... Agent: Nvidia Corporation

20150089199 - Rotate instructions that complete execution either without writing or reading flags: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution... Agent: Intel Corporation

20150089200 - Rotate instructions that complete execution either without writing or reading flags: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution... Agent: Intel Corporation

20150089201 - Rotate instructions that complete execution either without writing or reading flags: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution... Agent: Intel Corporation

20150089202 - System, method, and computer program product for implementing multi-cycle register file bypass: A system, method, and computer program product are provided for implementing a multi-cycle register file bypass mechanism. The method includes the steps of receiving a set of control bits, combining the set of control bits with a set of valid bits associated with previously issued instructions, and enabling a bypass... Agent: Nvidia Corporation

20150089203 - Latency reduction in distributed computing environments: Systems and methods that facilitate anticipatory execution and provision of possible instructions receivable by a computing environment are described herein. A state management component identifies the possible instructions, and defines a prediction space. A predictor component selects one or more possible instructions to be executed by a processor module. In... Agent:

20150089204 - Dynamically reconfigurable microprocessor: A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute instructions according to a first configuration setting, the fingerprint unit accumulates information about the instructions according to a mathematical operation to generate a result. The... Agent: Via Technologies, Inc.

20150089205 - Convert from zoned format to decimal floating point format: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating... Agent:

20150089206 - Convert to zoned format from decimal floating point format: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating... Agent:

20150089207 - Technique for counting values in a register: A parallel counter accesses data generated by an application and stored within a register. The register includes different segments that include different portions of the application data. The parallel counter is configured to count the number of values within each segment that have a particular characteristic in a parallel fashion.... Agent: Nvidia Corporation

20150089208 - Predictor data structure for use in pipelined processing: A predictor data structure is used for pipelined processing by a pipelined processor. The predictor data structure includes a predicted address to be used in return from execution of a selected instruction, and a predicted operating state associated with the predicted address. Based on determining a selected return instruction is... Agent:

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