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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
08/07/2014 > 14 patent applications in 11 patent subcategories.

20140223138 - Systems, apparatuses, and methods for performing conversion of a mask register into a vector register.: Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a mask register into a vector register in response to a single vector packed convert a mask register to a vector register instruction that includes a destination vector register operand, a source writemask register operand, and... Agent:

20140223140 - Systems, apparatuses, and methods for performing vector packed unary encoding using masks: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed unary encoding using masks in response to a single vector packed unary encoding using masks instruction that includes a source vector register operand, a destination writemask register operand, and an opcode are described.... Agent:

20140223139 - Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate: Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.... Agent:

20140223141 - Sharing tlb mappings between contexts: In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual... Agent:

20140223142 - Processor and compiler: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very... Agent: Panasonic Corporation

20140223143 - Load latency speculation in an out-of-order computer processor: Load latency speculation in an out-of-order computer processor, including: issuing a load instruction for execution, wherein the load instruction has a predetermined expected execution latency; issuing a dependent instruction wakeup signal on an instruction wakeup bus, wherein the dependent instruction wakeup signal indicates that the load instruction will be completed... Agent: International Business Machines Corporation

20140223144 - Load latency speculation in an out-of-order computer processor: Load latency speculation in an out-of-order computer processor, including: issuing a load instruction for execution, wherein the load instruction has a predetermined expected execution latency; issuing a dependent instruction wakeup signal on an instruction wakeup bus, wherein the dependent instruction wakeup signal indicates that the load instruction will be completed... Agent: International Business Machines Corporation

20140223145 - Configurable reduced instruction set core: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be... Agent: Intel Corporation

20140223146 - Blank bit and processor instructions employing the blank bit: Reading a value into a register, checking to see if the value is a NULL, and then jumping out of a loop if the value is a NULL is a common task that processors perform. To speed performance of such a task, a novel “blank bit” is added to the... Agent: Ixys Ch Gmbh

20140223147 - Systems and methods for virtual parallel computing using matrix product states: A virtual parallel computing system and method represents bits with matrices and computes over all input states in parallel through a sequence of matrix operations. The matrix operations relate to logic gate operators to carry out a function implementation that represents a problem to be solved. Initial matrices are prepared... Agent:

20140223148 - Method of entropy randomization on a parallel computer: Method, system, and computer program product for randomizing entropy on a parallel computing system using network arithmetic logic units (ALUs). In one embodiment, network ALUs on nodes of the parallel computing system pseudorandomly modify entropy data during broadcast operations through application of arithmetic and/or logic operations. That is, each compute... Agent: International Business Machines Corporation

20140223149 - Method of entropy randomization on a parallel computer: Method, system, and computer program product for randomizing entropy on a parallel computing system using network arithmetic logic units (ALUs). In one embodiment, network ALUs on nodes of the parallel computing system pseudorandomly modify entropy data during broadcast operations through application of arithmetic and/or logic operations. That is, each compute... Agent: International Business Machines Corporation

20140223150 - Information processing apparatus, information processing system, and stop method: An information processing apparatus includes a first preservation unit configured to preserve execution request information for information processing; an execution unit configured to execute one or more types of the information processing; an execution control unit configured to have the execution unit being capable of executing one of the types... Agent: Ricoh Company, Ltd.

20140223151 - Kernel execution for hybrid systems: A method for executing kernels in a hybrid system includes running a program on a host computer and identifying in an instruction stream of the program a first instruction including a function of a target classification. The method includes generating a first kernel including the function and transmitting the first... Agent: International Business Machines Corporation

  
07/31/2014 > 14 patent applications in 11 patent subcategories.
  
07/24/2014 > 23 patent applications in 15 patent subcategories.

20140208065 - Apparatus and method for mask register expand operation: An apparatus and method are described for expanding bits from a mask register in a processor and computing system with vector registers and vector data elements. For example, a method according to one embodiment includes the following operations: reading each mask register bit stored in a mask register, the mask... Agent:

20140208067 - Vector element rotate and insert under mask instruction: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the... Agent: International Business Machines Corporation

20140208066 - Vector generate mask instruction: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the... Agent: International Business Machines Corporation

20140208068 - Data compression and decompression using simd instructions: Compression and decompression of numerical data utilizing single instruction, multiple data (SIMD) instructions is described. The numerical data includes integer and floating-point samples. Compression supports three encoding modes: lossless, fixed-rate, and fixed-quality. SIMD instructions for compression operations may include attenuation, derivative calculations, bit packing to form compressed packets, header generation... Agent: Samplify Systems, Inc.

20140208069 - Simd instructions for data compression and decompression: An execution unit configured for compression and decompression of numerical data utilizing single instruction, multiple data (SIMD) instructions is described. The numerical data includes integer and floating-point samples. Compression supports three encoding modes: lossless, fixed-rate, and fixed-quality. SIMD instructions for compression operations may include attenuation, derivative calculations, bit packing to... Agent: Samplify Systems, Inc.

20140208071 - Adaptive service controller, system on chip and method of controlling the same: A system on chip (SOC) includes a slave device, a plurality of master devices, an interconnect device and a plurality of service controllers. The master devices generate requests to demand services from the slave device. The interconnect device is coupled to the slave device and the master devices through respective... Agent:

20140208070 - Systems and methods for interfacing master and slave processors: System and methods are provided. In one embodiment, a system includes a first processor comprising a serial peripheral interface (SPI) port, and a second processor. The system further includes a galvanic isolation barrier. The system additionally includes a SPI bridge comprising a first output pin control configured to control a... Agent: General Electric Company

20140208072 - User-level manager to handle multi-processing on many-core coprocessor-based systems: A method is disclosed to manage a multi-processor system with one or more multiple-core coprocessors by intercepting coprocessor offload infrastructure application program interface (API) calls; scheduling user processes to run on one of the coprocessors; scheduling offloads within user processes to run on one of the coprocessors; and affinitizing offloads... Agent: Nec Laboratories America, Inc.

20140208073 - Arithmetic branch fusion: A processor and method for fusing together an arithmetic instruction and a branch instruction. The processor includes an instruction fetch unit configured to fetch instructions. The processor may also include an instruction decode unit that may be configured to decode the fetched instructions into micro-operations for execution by an execution... Agent: Apple Inc.

20140208074 - Instruction scheduling for a multi-strand out-of-order processor: In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an... Agent:

20140208075 - Systems and method for unblocking a pipeline with spontaneous load deferral and conversion to prefetch: Apparatuses, systems, and a method for providing a processor architecture with a control speculative load are described. In one embodiment, a computer-implemented method includes determining whether a speculative load instruction encounters a long latency condition, spontaneously deferring the speculative load instruction if the speculative load instruction encounters the long latency... Agent:

20140208076 - Dfa compression and execution: A character class (CCL) memory containing simple CCLs represented by encoding contained symbols or minimum and maximum symbols of a range, complex CCLs represented by bit-masks indicating contained symbols, and equivalence class (EC) maps represented as tables of ED values for each symbol value. Determining a next DFA transition by... Agent: Lsi Corporation

20140208078 - Vector checksum instruction: A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an... Agent: International Business Machines Corporation

20140208077 - Vector floating point test data class immediate instruction: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand... Agent: International Business Machines Corporation

20140208079 - Vector galois field multiply sum and accumulate instruction: A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the corresponding element of the third operand to provide one or more products. The one or more products are exclusively ORed with each other and... Agent: International Business Machines Corporation

20140208080 - Apparatus and method for down conversion of data types: An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a... Agent:

20140208082 - Automated test platform: A segmented subsystem, for use within an automated test platform, includes a first subsystem segment configured to execute one or more instructions within the first subsystem segment. A second subsystem segment is configured to execute one or more instructions within the second subsystem segment. The first subsystem segment includes: a... Agent: Ltx-credence Corporation

20140208081 - Flowchart compiler for a compound complex instruction set computer (ccisc) processor architecture: Systems and methods herein provide for a compiler to create executable programs for a compound instruction based processor directly from flowcharts. In one embodiment, a system receives one or more flowchart diagram files that represent a computer program for a Compound CISC (CCISC) processor. The system identifies a flowchart symbol... Agent:

20140208083 - Multi-threaded logging: A data slot may be reserved for a first thread selected from a plurality of threads executed by a computer system. A memory of the computer system may comprise a plurality of log files and a next free data slot pointer. Each log file may comprise a plurality of data... Agent: Morgan Stanley

20140208084 - Compound complex instruction set computer (ccisc) processor architecture: A processor system includes a multichannel memory operable to store data values and a program memory operable to store Compound CISC (CCISC) instructions. The processor system also includes a processor operable to execute a computer program assembled with at least a portion of the compound CCISC instructions, to retrieve a... Agent:

20140208085 - Instruction and logic to efficiently monitor loop trip count: Logic and instruction to efficiently monitor loop trip count. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations... Agent:

20140208087 - Microprocessor architecture having extendible logic: A microprocessor architecture having extendible logic. One or more customized applications are available to the instruction pipeline. The customizable applications may include software, extension logic instruction or register, dynamically configurable hardware logic, or combinations of these. In order to enable the operating system to interface with the customized extension applications,... Agent: Synopsys, Inc.

20140208086 - Vector exception code: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The... Agent: International Business Machines Corporation

  
07/17/2014 > 14 patent applications in 8 patent subcategories.

20140201498 - Instruction and logic to provide vector scatter-op and gather-op functionality: Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset... Agent: Intel Corporation

20140201497 - Instruction for element offset calculation in a multi-dimensional array: An apparatus is described having functional unit logic circuitry. The functional unit logic circuitry has a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure. Each element of the first vector operand specifying the size of its respective dimension.... Agent:

20140201499 - Systems, apparatuses, and methods for performing conversion of a list of index values into a mask value: Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a list of index values into a mask value in response to a single vector packed conversion of a list of index values into a mask value instruction that includes a destination writemask register operand, a... Agent:

20140201500 - Controlling bandwidth allocations in a system on a chip (soc): In one embodiment, a fabric of a processor such as a system on a chip includes at least one data buffer including a plurality of entries each to store data to be transferred to and from a plurality of agents and to and from a memory, a request tracker to... Agent:

20140201501 - Dynamic accessing of execution elements through modification of issue rules: Embodiments of the invention relate to dynamically routing instructions to execution units based on detected errors in the execution units. An aspect of the invention includes a computer system including a processor having an instruction issue unit and a plurality of execution units. The processor is configured to detect an... Agent: International Business Machines Corporation

20140201504 - Functional unit capable of executing approximations of functions: A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit.... Agent:

20140201503 - Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second... Agent: Texas Instruments Incorporated

20140201502 - Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed butterfly horizontal cross add or subtract of packed data elements in response to a single vector packed butterfly horizontal cross add or subtract instruction that includes a destination vector register operand, a source vector register operand,... Agent:

20140201505 - Prediction-based thread selection in a multithreading processor: A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the... Agent:

20140201506 - Method for determining instruction order using triggers: A processing engine includes separate hardware components for control processing and data processing. The instruction execution order in such a processing engine may be efficiently determined in a control processing engine based on inputs received by the control processing engine. For each instruction of a data processing engine: a status... Agent:

20140201508 - Confidence threshold-based opposing branch path execution for branch prediction: Embodiments relate to confidence threshold-based opposing path execution for branch prediction. An aspect includes determining a branch prediction for a first branch instruction that is encountered during execution of a first thread, wherein the branch prediction indicates a primary path and an opposing path for the first branch instruction. Another... Agent: International Business Machines Corporation

20140201509 - Switch statement prediction: Methods and branch predictors for predicting a target location of a jump table switch statement in a program. The method includes continuously monitoring instructions at the branch predictor to determine if they write to registers used to store an input variable to a jump table switch statement. Any update to... Agent: Imagination Technologies, Ltd.

20140201507 - Thread selection at a processor based on branch prediction confidence: A processor employs one or more branch predictors to issue branch predictions for each thread executing at an instruction pipeline. Based on the branch predictions, the processor determines a branch prediction confidence for each of the executing threads, whereby a lower confidence level indicates a smaller likelihood that the corresponding... Agent: Advanced Micro Devices, Inc.

20140201510 - System, apparatus and method for generating a loop alignment count or a loop alignment mask: A loop alignment instruction indicates a base address of an array as a first operand, an iteration limit of a loop as a second operand, and a destination. The loop contains iterations and each iteration includes a data element of the array. A processor receives the loop alignment instruction, decodes... Agent:

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