Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) inventions

20080104366 - Semiconductor chip: Disclosed herein is a semiconductor chip including at least two processing apparatuses which comply with the same interface specifications and which differ in internal structure, wherein at least one of the processing apparatuses is constituted functionally to replace at least one processing apparatus.... Agent: Rader Fishman & Grauer PLLC

20080104367 - Collective network for computer structures: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices ate included that interconnect... Agent: Scully, Scott, Murphy & Presser, P.C.

20080104368 - Storage element having data protection functionality: A storage element has data protection functionality for receiving a data-writing and a data-reading from a functional module. The storage element comprises a storage unit that has a memory region with a predetermined capacity for storing the data and stores the data written by the functional module, a data amount... Agent: Staas & Halsey LLP

20080104365 - Configurable processor design apparatus and design method, library optimization method, processor, and fabrication method for semiconductor device including processor: A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080104369 - Network interface card for use in parallel computing systems: A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises... Agent: Koestner Bertani LLP

20080104370 - Risc type of cpu and compiler to produce object program executed by the same: A RISC type of CPU is provided to execute an object program in which a stack area is used. The CPU is configured to have a return instruction based on an operand at which an open size is specified and to perform the return instruction when the stack area is... Agent: Harness, Dickey & Pierce, P.L.C

20080104371 - Method and system using hardware assistance for continuance of trap mode during or after interruption sequences: A method, system, apparatus, and computer program product is presented for processing instructions. A processor is able to receive multiple types of interruptions while executing instructions, such as aborts, faults, interrupts, and traps. A set of processor fields are used to indicate whether or not one or more trap modes... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080104372 - Method, apparatus and computer program for executing a program: There is provided a method for executing a program comprising a function call and one or more subsequent instructions. The method comprises processing, on a first thread, a function defined by the function call, the function having one or more programmer predefined typical return values. For each predefined return value,... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080104373 - Scheduling technique for software pipelining: An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple sub-graphs of a DDG) which are independent, and substantially identical. The improvement in... Agent: Ibm Corp. (wsm) C/o Winstead Sechrest & Minick P.C.

20080104374 - Hardware sorter: A hardware sorter comprises a comparator matrix (104) for checking if each number in an unsorted array input (102) is at least equal to each other number, a set of column summers (108) for counting the number of numbers that each number is at least equal to, a decoder array... Agent: Motorola, Inc.

20080104375 - Programmable processor and method with wide operations: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are... Agent: Townsend And Townsend And Crew, LLP

20080104376 - Method and apparatus for performing group instructions: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different... Agent: Townsend And Townsend And Crew, LLP

20080104377 - Method and system of overload control in packetized communication networks: In a method for processor overload control in a wireless or other network, a processor occupancy level (“PO”) of a network processing unit is monitored and compared to a target PO. If the measured PO exceeds the target PO, one or more network load sources are controlled to reduce the... Agent: Mccormick, Paulding & Huber LLP

20080098200 - Two dimensional addressing of a matrix-vector register array: A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2,... Agent: Schmeiser, Olsen & Watts

20080098201 - Parallel data processing apparatus: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another.... Agent: Glenn Patent Group

20080098203 - Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry havingf fixed, application specific computational elements: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC... Agent: Nixon Peabody, LLP

20080098202 - Coupling a general purpose processor to an application specific instruction set processor: Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP... Agent: Louis Paul Herzberg

20080098205 - Apparatus and methods for stabilization of processors, operating systems and other hardware and/or software configurations: Apparatus and methods for converting a processor, having a plurality of states and being operative to execute software operations stored in a memory device, into a self-stabilizing processor, comprising providing self-stabilizing watchdog hardware that, with given timing, interacts with the processor, in accordance with an interaction sequence that includes at... Agent: The Nath Law Group

20080098204 - Method and apparatus for improving the efficiency of a processor instruction pipeline: A system and method are disclosed which may include providing a processor instruction pipeline having a main line and a branch line; executing at least one wait cycle for at least one wait instruction in said pipeline; and advancing at least selected instructions, that are initially located subsequent to at... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20080098206 - Plotting device and plotting method: A reference address generator receives UV coordinate values from a shader, converts the value into a reference address for referring to a texture, and refers to a texture map or an instruction map stored in a texture memory based upon the reference address. The value referred to by the texture... Agent: Katten Muchin Rosenman LLP

20080098207 - Analyzing diagnostic data generated by multiple threads within an instruction stream: A diagnostic method for outputting diagnostic data relating to processing of instruction streams stemming from a computer program, at least some of said instructions streams comprising multiple threads is disclosed. The method comprises the steps of: (i) receiving diagnostic data; (ii) reordering said received diagnostic data in dependence upon reordering... Agent: Nixon & Vanderhye, PC

20080098208 - Analyzing and transforming a computer program for executing on asymmetric multiprocessing systems: A method is disclosed for transforming a portion of a computer program comprising a list of sequential instructions comprising control code and data processing code and a program separation indicator indicating a point where said sequential instructions may be divided to form separate sections that are capable of being separately... Agent: Nixon & Vanderhye, PC

20080091917 - Apparatus and method for directing micro architectural memory region accesses: In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may... Agent: Trop, Pruner & Hu, P.C.

20080091919 - Multi-channel multi-media integrated circuit and method thereof: The present invention discloses a multi-channel multi-media data processing method, comprising the steps of: providing a demodulator circuit and a multi-media processing circuit, the multi-media processing circuit including a DRAM; receiving multi-channel analog signals, and performing analog-to-digital conversion and demodulation on the signals by the demodulator circuit; storing the converted... Agent: Tung & Associates Suite 120

20080091918 - Method and data processing system for microprocessor communication in a cluster-based multi-processor system: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each... Agent: Bracewell & Patterson, L.L.P.

20080091920 - Transferring data between registers in a risc microprocessor architecture: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A... Agent: Henneman & Associates, PLC

20080091921 - Data prefetching in a microprocessing environment: Systems and methods for prefetching data in a microprocessor environment are provided. The method comprises decoding a first instruction; determining if the first instruction comprises both a load instruction and embedded prefetch data; processing the load instruction; and processing the prefetch data, in response to determining that the first instruction... Agent: Stephen C. Kaufman IBM Corporation

20080091922 - Data stream prefetching in a microprocessor: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch... Agent: Ibm Corporation (dwl) C/o Lally & Lally, L.L.P.

20080091923 - Register-based instruction optimization for facilitating efficient emulation of an instruction stream: A register-based instruction optimization is provided for facilitating efficient emulation of a target instruction stream. The optimization includes for at least one instruction in a frequently executed sequence of target instructions: confirming that at least one register is marked as a read-only register for the sequence; confirming that each register... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080091924 - Vector processor and system for vector processing: An embodiment of a vector processor includes a vector control and distribution unit and lanes. In operation, the vector control and distribution unit receives vector instructions, decomposes the vector instructions into vector element operations, and forwards the vector element operations for execution. Each lane proceeds to execute vector element operations... Agent: Hewlett Packard Company

20080091925 - Method and software for group floating-point arithmetic operations: Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple data elements, the instructions selected from an instruction set that includes group... Agent: Mcdermott Will & Emery LLP

20080091926 - Optimization of a target program: A method and apparatus for optimizing a target program including a pattern of instructions to be replaced. The method is performed by execution of program code by a processor of an information processing apparatus that includes an output device and a computer readable storage medium storing the program code. At... Agent: Schmeiser, Olsen & Watts

20080091927 - Method and device for a switchover in a computer system having at least two processing units: A method and device for switching over in a computer system having at least two processing units, a switchover means and a compare means, switching over taking place between at least two operating modes, and a first operating mode corresponding to a compare mode, and a second operating mode corresponding... Agent: Kenyon & Kenyon LLP

20080091928 - Branch lookahead prefetch for microprocessors: A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and... Agent: Ibm Corporation (jvm)

20080086621 - Command supply device: A command supply device is provided that efficiently supplies a command sequence that forms a loop. The command supply device includes a loop command buffer in which the command supply device accumulates a first partial command sequence that is a head part of a first command sequence repeatedly supplied to... Agent: Greenblum & Bernstein, P.L.C

20080086622 - Replay reduction for power saving: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20080086623 - Strongly-ordered processor with early store retirement: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20080086625 - Apparatus and method for updating the function of monitor: The present invention provides an apparatus for updating the function of a monitor and the method thereof. The method comprises: coupling a scale controller and a memory device of at least a monitor to a microcontroller; controlling the microcontroller to send a programming activation signal in a first signal format... Agent: North America Intellectual Property Corporation

20080086624 - Latch to block short path violation: An integrated circuit 2 includes processing pipeline stages formed of an input register 8, processing circuit 10′, 10″ and an output register 12. The output register 12 employs speculative sampling and uses a subsequent speculation period during which any change in its input is detected and used to indicate a... Agent: Nixon & Vanderhye, Pc

20080086626 - Inter-processor communication method: Inter-processor communication systems and methods that define within the instruction set of the microprocessor a command for directing the microprocessor to relinquish control over at least one of the microprocessor's internal registers. The microprocessor may then signal a communication interface that collects data from external sources. The communication interface takes... Agent: Ropes & Gray LLP Patent Docketing 39/41

20080086627 - Methods and apparatus to analyze computer software: Methods and apparatus to analyze computer software are disclosed. The disclosed methods and apparatus may be used to verify and validate computer software. An example method includes receiving from a software test engine a definition of a graphical user interface associated with an application, receiving a user input indicating a... Agent: Hanley, Flight & Zimmerman, Llc