|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) November recently filed with US Patent Office 11/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/29/2012 > 7 patent applications in 5 patent subcategories. recently filed with US Patent Office
20120303933 - tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms: The present invention relates to a processor which comprises processing elements that execute instructions in parallel and are connected together with point-to-point communication links called data communication links (DCL). The instructions use DCLs to communicate data between them. In order to realize those communications, they specify the DCLs from which... Agent:
20120303932 - Runtime reconfigurable dataflow processor: A processor includes a plurality of processing tiles, wherein each tile is configured at runtime to perform a configurable operation. A first subset of tiles are configured to perform in a pipeline a first plurality of configurable operations in parallel. A second subset of tiles are configured to perform a... Agent: New York University
20120303934 - Method and apparatus for generating an enhanced processor resync indicator signal using hash functions and a load tracking unit: A method and apparatus are described for generating a signal to resync a processor. In one embodiment, a particular load operation is picked from a load queue in the processor, and the particular load operation is completed out of order with respect to other load operations in the load queue.... Agent: Advanced Micro Devices, Inc.
20120303936 - Data processing system with latency tolerance execution: In a processor having an instruction unit, a decode/issue unit, and execution queues configured to provide instructions to correspondingly different types execution units, a method comprises maintaining a duplicate free list for the execution queues. The duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when... Agent: Freescale Semiconductor, Inc.
20120303935 - Microprocessor systems and methods for handling instructions with multiple dependencies: A processor includes an instruction unit which provides instructions for execution by the processor, a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions, and a plurality of execution queues coupled to the decode/issue unit. Each issued instruction from the decode/issue unit is stored into... Agent:
20120303937 - Computer system and control method thereof: A computer system used to execute an application includes a motion sensing unit, a processor and an instruction transfer unit. The motion sensing unit senses a gesture of a human body and generates an input instruction based on the gesture. The processor executes the application (or a game). The instruction... Agent:
20120303938 - Performance in predicting branches: A method, data processing system, and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is... Agent: International Business Machines Corporation11/22/2012 > 11 patent applications in 9 patent subcategories. recently filed with US Patent Office
20120297163 - Automatic kernel migration for heterogeneous cores: A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a... Agent:
20120297164 - Virtualization in a multi-core processor (mcp): This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of... Agent: International Business Machines Corporation
20120297165 - Electronic device and method for data processing using virtual register mode: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit... Agent: Texas Instruments Incorporated
20120297166 - Stack processor using a ferroelectric random access memory (f-ram) having an instruction set optimized to minimize memory fetch operations: A stack processor using a non-volatile, ferroelectric random access memory (F-RAM) for both code and data space. The stack processor is operative in response to as many as 64 possible instructions based upon a 16 bit word. Each of the instructions in the 16 bit word comprises 3 five bit... Agent: Ramtron International Corporation
20120297167 - Efficient call return stack technique: A processor, method, and medium for implementing a call return stack within a pipelined processor. A stack head register is used to store a copy of the top entry of the call return stack, and the stack head register is accessed by the instruction fetch unit on each fetch cycle.... Agent:
20120297168 - Processing instruction grouping information: Processing instruction grouping information is provided that includes: reading addresses of machine instructions grouped by a processor at runtime from a buffer to form an address file; analyzing the address file to obtain grouping information of the machine instructions; converting the machine instructions in the address file into readable instructions;... Agent: International Business Machines Corporation
20120297169 - Data processing apparatus, control method therefor, and non-transitory computer-readable storage medium: A data processing apparatus which sequentially executes a verification process so as to recognize a target object, comprising: an obtaining unit configured to obtain dictionary data to be referred to in the verification process; a holding unit configured to hold a plurality of dictionary data; a verification unit configured to... Agent: Canon Kabushiki Kaisha
20120297170 - Decentralized allocation of resources and interconnnect structures to support the execution of instruction sequences by a plurality of engines: A method for decentralized resource allocation in an integrated circuit. The method includes receiving a plurality of requests from a plurality of resource consumers of a plurality of partitionable engines to access a plurality resources, wherein the resources are spread across the plurality of engines and are accessed via a... Agent: Soft Machines, Inc.
20120297171 - Methods for generating code for an architecture encoding an extended register specification: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.... Agent: International Business Machines Corporation
20120297172 - Multi-threaded processes for opening and saving documents: Tools and techniques are described for multi-threaded processing for opening and saving documents. These tools may provide load processes for reading documents from storage devices, and for loading the documents into applications. These tools may spawn a load process thread for executing a given load process on a first processing... Agent: Microsoft Corporation
20120297173 - Debugger system, method and computer program product for debugging instructions: Debugger system, method and computer program product for debugging instructions. The method for debugging instructions may include: receiving, by a debugger module, a group of instructions that are stored in a non-volatile memory module and is scheduled to be executed by a processor of a device; determining whether the group... Agent: Freescale Semiconductor, Inc.11/15/2012 > 8 patent applications in 8 patent subcategories. recently filed with US Patent Office
20120290814 - Communication between internal and external processors: Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided. In one or more embodiments, conflicts in accessing the memory array are reduced by interfacing an external processor, such as a memory controller, with... Agent: Micron Technology, Inc.
20120290815 - Data processing apparatus and data processing method: A data processing apparatus causes multiple processors to carry out a first data process in parallel, and when storing the data processed in parallel in a storage unit, converts the addresses of the data into addresses in the storage unit based on the data cache size of the multiple processors... Agent: Canon Kabushiki Kaisha
20120290816 - Optimized scalar promotion with load and splat simd instructions: Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an identification of scalar and SIMD operations in an original code representation. The original code representation may be modified to insert the vector operation-splat... Agent: International Business Machines Corporation
20120290817 - Branch target storage and retrieval in an out-of-order processor: A processor configured to facilitate transfer and storage of predicted targets for control transfer instructions (CTIs). In certain embodiments, the processor may be multithreaded and support storage of predicted targets for multiple threads. In some embodiments, a CTI branch target may be stored by one element of a processor and... Agent: Oracle International Corporation
20120290818 - Split scheduler: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support... Agent:
20120290819 - Dsp block with embedded floating point structures: A specialized processing block includes a first floating-point arithmetic operator stage, a second floating-point arithmetic operator stage, and configurable interconnect within the specialized processing block for routing signals into and out of each of the first and second floating-point arithmetic operator stages. In some embodiments, the configurable interconnect may be... Agent: Altera Corporation
20120290820 - Suppression of control transfer instructions on incorrect speculative execution paths: Techniques are disclosed relating to a processor that is configured to execute control transfer instructions (CTIs). In some embodiments, the processor includes a mechanism that suppresses results of mispredicted younger CTIs on a speculative execution path. This mechanism permits the branch predictor to maintain its fidelity, and eliminates spurious flushes... Agent: Oracle International Corporation
20120290821 - Low-latency branch target cache: Techniques and structures are disclosed relating to a branch target cache (BTC) in a processor. In one embodiment, the BTC is usable to predict whether a control transfer instruction is to be taken, and, if applicable, a target address for the instruction. The BTC may operate in conjunction with a... Agent:11/08/2012 > 4 patent applications in 4 patent subcategories. recently filed with US Patent Office
20120284487 - Vector slot processor execution unit for high speed streaming inputs: A vector slot processor that is capable of supporting multiple signal processing operations for multiple demodulation standards is provided. The vector slot processor includes a plurality of micro execution slot (MES) that performs the multiple signal processing operations on the high speed streaming inputs. Each of the MES includes one... Agent: Saankhya Labs Private Limited
20120284488 - Methods and apparatus for constant extension in a processor: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant... Agent: Qualcomm Incorporated
20120284489 - Methods and apparatus for constant extension in a processor: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant... Agent: Qualcomm Incorporated
20120284490 - Working set profiler: A working set profiler can monitor an execution of a program or can monitor a user-specified portion of a program to identify methods executed within the monitored execution and associate memory page accesses with each of the identified methods. Memory page accesses are categorized as shared or exclusive, where a... Agent: Microsoft Corporation11/01/2012 > 8 patent applications in 6 patent subcategories. recently filed with US Patent Office
20120278590 - Reconfigurable processing system and method: A reconfigurable processor is provided. The reconfigurable processor includes a plurality of functional blocks configured to perform corresponding operations. The reconfigurable processor also includes one or more data inputs coupled to the plurality of functional blocks to provide one or more operands to the plurality of functional blocks, and one... Agent: Shanghai Xin Hao Micro Electronics Co. Ltd.
20120278589 - Storage system comprising multiple microprocessors and method for sharing processing in this storage system: The present invention provides a storage system in which each microprocessor is able to execute synchronous processing and asynchronous processing in accordance with the operating status of the storage system. Any one attribute, from among multiple attributes (operating modes) prepared beforehand, is set in each microprocessor in accordance with the... Agent: Hitachi, Ltd.
20120278591 - Crossbar switch module having data movement instruction processor module and methods for implementing the same: A microprocessor is provided that has a datapath that is split into upper and lower portions. The microprocessor includes a centralized crossbar switch module having a single data movement module. The data movement module is capable of processing instructions that require operands to be exchanged between upper and lower 64-bit... Agent: Advanced Micro Devices, Inc.
20120278592 - Microprocessor systems and methods for register file checkpointing: In a processor, a decode unit identifies instructions needing a checkpoint and enables selected checkpoints, and a register file unit includes a plurality of architectural registers; a first set of checkpoint registers corresponding to a first checkpoint, wherein each checkpoint register of the first set corresponds to a corresponding architectural... Agent:
20120278593 - Low complexity out-of-order issue logic using static circuits: Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in... Agent: Arizona Technology Enterprises, LLC
20120278594 - Performance bottleneck identification tool: A computer program product for identifying bottlenecks includes a computer readable storage medium with stored computer readable program instructions. The computer readable program instructions, when executed, provide a data collector module, a mapper module, and an analyzer module that are collectively configured to read mapped data and configuration files, and... Agent: International Business Machines Corporation
20120278595 - Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall: During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of... Agent: International Business Machines Corporation
20120278596 - Apparatus and method for checkpoint repair in a processing device: A data processing device maintains register map information that maps accesses to architectural registers, as identified by instructions being executed, to physical registers of the data processing device. In response to determining that an instruction, such as a speculatively-executing conditional branch, indicates a checkpoint, the data processing device stores the... Agent: Freescale Semiconductor, Inc.Previous industry: Electrical computers and digital processing systems: memory
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