|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All
10/2012 | Recent | 15: Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) October categorized by USPTO classification 10/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 10/25/2012 > 8 patent applications in 7 patent subcategories. categorized by USPTO classification
20120272040 - Enhanced modularity in heterogeneous 3d stacks: A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common... Agent: International Business Machines Corporation
20120272041 - Multiprocessing of data sets: Various arrangements for processing data sets using multiple processors are presented. A plurality of constraints may be received by a computer system. Each constraint may identify a data relationship that requires a subset of records of one or more data sets to be processed by a same processing device. A... Agent: Oracle International Corporation
20120272042 - Distributed micro instructions set processor architecture for high-efficiency signal processing: A wireless communication base station comprising a plurality of application specific instruction set processors (ASISPs) configured to support one or more processes hosted by the base station, and to track process state information associated with each of the processes; and a memory configured to store the tracked process state information,... Agent: Intel Mobile Communications Gmbh
20120272044 - Processor for executing highly efficient vliw: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the... Agent: Panasonic Corporation
20120272043 - Request coalescing for instruction streams: Sequential fetch requests from a set of fetch requests are combined into longer coalesced requests that match the width of a system memory interface in order to improve memory access efficiency for reading the data specified by the fetch requests. The fetch requests may be of different classes and each... Agent:
20120272045 - Control method and system of multiprocessor: A control method and a system for dispatching the execution sequence of the processes in a multiprocessors system so as to dispatch an operation sequence for executing different operation programs by a monitoring processor and a plurality of target processors. The monitoring processor obtains operation status of other processors from... Agent: Feature Integration Technology Inc.
20120272046 - Vector completion mask handling: Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for... Agent:
20120272047 - Method and apparatus for shuffling data: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the... Agent:10/18/2012 > 10 patent applications in 9 patent subcategories. categorized by USPTO classification
20120265964 - Data processing device and data processing method thereof: Disclosed is a data processing device capable of efficiently performing an arithmetic process on variable-length data and an arithmetic process on fixed-length data. The data processing device includes first PEs of SIMD type, SRAMs provided respectively for the first PEs, and second PEs. The first PEs each perform an arithmetic... Agent: Renesas Electronics Corporation
20120265965 - Processing bypass directory tracking system and method: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to... Agent:
20120265966 - Processor with increased efficiency via early instruction completion: Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or... Agent: Advanced Micro Devices, Inc.
20120265967 - Implementing instruction set architectures with non-contiguous register file specifiers: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.... Agent: International Business Machines Corporation
20120265968 - Locating bottleneck threads in multi-thread applications: A method for identifying a consumer-producer pattern in a multi-threaded application includes obtaining synchronization event data of the multi-threaded application, and identifying the consumer-producer communication pattern from the synchronization event data.... Agent:
20120265969 - Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions: A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an... Agent: International Business Machines Corporation
20120265970 - System and method of indirect register access: Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect... Agent: Micron Technology, Inc.
20120265971 - Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions: A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least... Agent: International Business Machines Corporation
20120265972 - Method and apparatus and record carrier: Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a... Agent:
20120265973 - High reliability processor system: A method of testing the integrity of microprogramming within a computer processor employs a test calculation designed to exercise instructions and to reveal errors in those instructions. The problem of testing instructions using the very instructions which may possibly be corrupt is addressed by developing a signature passed from instruction... Agent:10/11/2012 > 15 patent applications in 11 patent subcategories. categorized by USPTO classification
20120260061 - Data processing apparatus and method for performing vector operations: A data processing apparatus having processing circuitry, a scalar register bank and a vector register bank, including decoding circuitry arranged to decode a sequence of instructions to generate control signals for the processing circuitry. The decoding circuitry is responsive to a decode modifier instruction within the sequence of instructions to... Agent: Arm Limited
20120260062 - System and method for providing dynamic addressability of data elements in a register file with subword parallelism: A method and system for providing dynamic addressability of data elements in a vector register file with subword parallelism. The method includes the steps of: determining a plurality of data elements required for an instruction; storing an address for each of the data elements into a pointer register where the... Agent: International Business Machines Corporation
20120260063 - Modular, detachable compute leaf for use with computing system: A detachable, logic leaf module having dendritic projections on a surface is connected to a recessed area on the surface of a cluster interface board. The projections are used for electrically connecting the logic module device to the cluster interface board or the like, the projections on the surface of... Agent: Endicott Interconnect Technologies, Inc.
20120260066 - Heterogeneous isa microprocessor that preserves non-isa-specific configuration state when reset to different isa: A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second... Agent: Via Technologies, Inc.
20120260064 - Heterogeneous isa microprocessor with shared hardware isa registers: A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program and a plurality of... Agent: Via Technologies, Inc.
20120260065 - Multi-core microprocessor that performs x86 isa and arm isa machine language program instructions by hardware translation into microinstructions executed by common execution pipeline: A microprocessor includes a plurality of processing cores each including a hardware instruction translator that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor. The microinstructions are encoded in... Agent: Via Technologies, Inc.
20120260068 - Apparatus and method for handling of modified immediate constant during instruction translation: An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based... Agent: Via Technologies, Inc.
20120260067 - Microprocessor that performs x86 isa and arm isa machine language program instructions by hardware translation into microinstructions executed by common execution pipeline: A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner from the x86 and ARM instructions. An execution pipeline executes the microinstructions to generate x86/ARM-defined results. The microinstructions are distinct from the results... Agent: Via Technologies, Inc.
20120260069 - Processor including age tracking of issue queue instructions: An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age... Agent: International Business Machines Corporation
20120260070 - Thread selection for multithreaded processing: A multithreading processor 4 interleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors performance parameters of individual program threads to generate performance values. Issue control circuitry 28 reads these performance values to determine which program thread is next selected to be... Agent:
20120260071 - Conditional alu instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor: An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction... Agent: Via Technologies, Inc.
20120260072 - Register allocation in rotation based alias protection register: A system may comprises an optimizer/scheduler to schedule on a set of instructions, compute a data dependence, a checking constraint and/or an anti-checking constraint for the set of scheduled instructions, and allocate alias registers for the set of scheduled instructions based on the data dependence, the checking constraint and/or the... Agent:
20120260073 - Emulation of execution mode banked registers: A microprocessor includes processor modes comprising a user mode and a plurality of exception modes. An execution unit performs arithmetic operations on operands specified by program instructions. A first set of storage elements holds a first subset of the operands and provides them to the execution unit coupled thereto. A... Agent: Via Technologies, Inc.
20120260075 - Conditional alu instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor: A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the shift operation on the first source operand to generate the first result and a carry flag value and updates a non-architectural carry flag... Agent: Via Technologies, Inc.
20120260074 - Efficient conditional alu instruction in read-port limited register file microprocessor: A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction... Agent: Via Technologies, Inc.10/04/2012 > 13 patent applications in 8 patent subcategories. categorized by USPTO classification
20120254585 - Method and apparatus for fast branch-free vector division computation: Methods and apparatus for double precision division/inversion vector computations on Single Instruction Multiple Data (SIMD) computing platforms are described. In one embodiment, an input argument is represented by an exponent portion and a fraction portion. These portions are scaled, inverted, and multiplied to generate an inverse version of the input... Agent:
20120254586 - Quantum and digital processor hybrid systems and methods to solve problems: Quantum processors and classical computers are employed together to solve computational problems. The classical computer may include a parameter learning module that produces a set of parameters. The quantum processor may be configured with the set of parameters to define a problem Hamiltonian and operated to perform adiabatic quantum computation... Agent: D-wave Systems Inc.
20120254587 - Accelerator engine commands submission over an interconnect link: An apparatus and method of submitting hardware accelerator engine commands over an interconnect link such as a PCI Express (PCIe) link. In one embodiment, the mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The mechanism provides an interface compatible with other... Agent: International Business Machines Corporation
20120254589 - System, apparatus, and method for aligning registers: Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination.... Agent:
20120254588 - Systems, apparatuses, and methods for blending two source operands into a single destination using a writemask: Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a... Agent:
20120254594 - Hardware assist thread for increasing code parallelism: Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already... Agent: International Business Machines Corporation
20120254590 - System and technique for a processor having a staged execution pipeline: A technique includes receiving a request from a processor to retrieve a first instruction from a memory for a staged execution pipeline. The technique includes selectively retrieving the first instruction from the memory in response to the request based on a determination of whether the processor will execute the first... Agent:
20120254592 - Systems, apparatuses, and methods for expanding a memory source into a destination register and compressing a source register into a destination memory location: Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the... Agent:
20120254593 - Systems, apparatuses, and methods for jumps using a mask register: Embodiments of systems, apparatuses, and methods for performing a jump instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a conditional jump to an address of a target instruction when all of bits of a writemask are zero, wherein the address of... Agent:
20120254591 - Systems, apparatuses, and methods for stride pattern gathering of data elements and stride pattern scattering of data elements: Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit... Agent:
20120254595 - Processor, information processing apparatus and control method thereof: Instructions decoded by the instruction decoding part are issued to an arithmetic and logic part, a consumption current value that has been consumed by the arithmetic and logic part with instructions issued during a first predetermined period and a consumption current estimated value for a current that is consumed by... Agent: Fujitsu Limited
20120254596 - Method and system for controlling message traffic between two processors: A system and method for controlling messaging between a first processor and a second processor is disclosed. The second processor controls one or more peripheral devices on behalf of a plurality of predetermined tasks being executed by the first processor. The system includes a message control module that receives an... Agent: Denso International America, Inc.
20120254597 - Branch-and-bound on distributed data-parallel execution engines: A distributed data-parallel execution (DDPE) system splits a computational problem into a plurality of sub-problems using a branch-and-bound algorithm, designates a synchronous stop time for a “plurality of processors” (for example, a cluster) for each round of execution, processes the search tree by recursively using a branch-and-bound algorithm in multiple... Agent: Microsoft CorporationPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20150416:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.
Results in 0.61697 seconds