|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) September class, title,number 09/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/27/2012 > 10 patent applications in 7 patent subcategories. class, title,number
20120246444 - Reconfigurable processor, apparatus, and method for converting code: Provided is an apparatus and method capable of processing code to which a software pipelining is not applicable, in a CGA mode. The apparatus may include a processing unit that has a very long instruction word (VLIW) mode and a coarse-grained array (CGA) mode, and an adjusting unit configured to... Agent:
20120246445 - Central processing unit and microcontroller: A program data area 38 storing program data is provided in an internal memory unit that a control circuit 31 of a CPU 3 can directly red from. The program data is constituted by instructions each comprising an instruction information part and an operand (i.e., a complementary information part) for... Agent:
20120246446 - Dynamically determining the profitability of direct fetching in a multicore architecture: Technologies are generally described herein for determining a profitability of direct fetching in a multicore processor. The multicore processor may include a first and a second tile. The first tile may include a first core and a first cache. The second tile may include a second core, a second cache,... Agent:
20120246448 - Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines: A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a... Agent: Soft Machines, Inc.
20120246447 - Region-weighted accounting of multi-threaded processor core according to dispatch state: According to one embodiment of the present disclosure, an approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational logic determines whether one of the multiple threads is dispatching an instruction and, if so, computes a dispatch weighting value using... Agent: International Business Machines Corporation
20120246449 - Method and apparatus for efficient loop instruction execution using bit vector scanning: A method, apparatus and computer program product for performing efficient loop instruction execution using bit vector scanning is presented. A bit vector is scanned, each bit in the bit vector representing at least one of a feature and a conditional status. The presence of a bit of said bit vector... Agent: Avaya Inc.
20120246450 - Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines: A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates... Agent: Soft Machines, Inc.
20120246451 - Processing long-latency instructions in a pipelined processor: There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some short-latency instructions and some long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed... Agent: Imagination Technologies, Ltd.
20120246452 - Signature update by code transformation: Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a program which includes at least the instruction sequence.... Agent: Infineon Technologies Ag
20120246453 - Method and apparatus for enhancing scheduling in an advanced microprocessor: Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining... Agent:09/20/2012 > 11 patent applications in 10 patent subcategories. class, title,number
20120239905 - Multi-core distributed processing for machine vision applications: Embodiments of an apparatus including a first processor core having a local agent running thereon, the agent comprising a local process and a proxy agent and a second processor core having a remote agent running thereon, the remote agent being an instance of the local agent. A shared memory wherein... Agent: Microscan Systems, Inc.
20120239906 - Launching a secure kernel in a multiprocessor system: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated.... Agent:
20120239907 - Active memory command engine and method: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine,... Agent: Micron Technology, Inc.
20120239908 - Dual thread processor: Pipeline processor architectures, processors, and methods are provided. A described processor includes thread allocation counters for corresponding processor threads. For example, a first counter is configured to store a first processor time allocation that controls first periods of processor time for a first processor thread, the first processor thread retaining... Agent:
20120239909 - Systems and methods for voting among parallel threads: One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread... Agent:
20120239910 - Conditional extract instruction for processing vectors: The described embodiments include a vector processor that executes a ConditionalExtract instruction. In the described embodiments, the processor receives an input scalar variable, an input vector, and a predicate vector, wherein each of the vectors has N elements. The processor then executes the ConditionalExtract instruction, which causes the processor to... Agent: Apple Inc.
20120239911 - Value check instruction for processing vectors: The described embodiments include a processor that executes a ValueCheck instruction. In the described embodiments, the processor receives an input vector and a predicate vector, each including N elements. The processor then executes a ValueCheck instruction, which causes the processor to generate a result vector. When generating the result vector,... Agent: Apple Inc.
20120239912 - Instruction processing method, instruction processing apparatus, and instruction processing program: An instruction processing method includes generating a translated code block for an instruction, among instructions included in a target program to be executed and for which a number of executions through sequential interpretation is greater than or equal to a threshold, and storing the generated translated code block in a... Agent: Fujitsu Limited
20120239913 - Diagnosing code using single step execution: A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a... Agent:
20120239914 - Multithreaded parallel execution device, broadcast stream playback device, broadcast stream storage device, stored stream playback device, stored stream re-encoding device, integrated circuit, multithreaded parallel execution method, and multithreaded com: When a temporary data storage unit 104 stores a value of “3” and an iteration number of “3”, and a data updating management unit 103 receives a value of “2” in combination with an iteration number of “2”, a data updating management unit 103 determines not to overwrite information in... Agent:
20120239915 - Interrupt handling: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal... Agent:09/13/2012 > 6 patent applications in 6 patent subcategories. class, title,number
20120233441 - Multi-threaded instruction buffer design: An instruction buffer for a processor configured to execute multiple threads is disclosed. The instruction buffer is configured to receive instructions from a fetch unit and provide instructions to a selection unit. The instruction buffer includes one or more memory arrays comprising a plurality of entries configured to store instructions... Agent:
20120233442 - Return address prediction in multithreaded processors: Techniques and structures are disclosed relating to predicting return addresses in multithreaded processors. In one embodiment, a processor is disclosed that includes a return address prediction unit. The return address prediction unit is configured to store return addresses for different ones of a plurality of threads executable on the processor.... Agent:
20120233443 - Processor to execute shift right merge instructions: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the... Agent:
20120233444 - Mixed size data processing operation: A data processing system 2 includes a processor core 4 and a memory 6. The processor core 4 includes processing circuitry 12, 14, 16, 18, 26 controlled by control signals generated by decoder circuitry 24 which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions... Agent:
20120233445 - Multi-thread processors and methods for instruction execution and synchronization therein and computer program products thereof: Methods for instruction execution and synchronization in a multi-thread processor are provided, wherein in the multi-thread processor, multiple threads are running and each of the threads can simultaneously execute a same instruction sequence. A source code or an object code is received and then compiled to generate the instruction sequence.... Agent: Via Technologies, Inc.
20120233446 - Program-instruction-controlled instruction flow supervision: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature... Agent: Infineon Technologies Ag09/06/2012 > 5 patent applications in 5 patent subcategories. class, title,number
20120226890 - Accelerator and data processing method: The process speed and the power efficiency are improved while accomplishing downsizing by configuring an integrated hard-wired logic controller by a hard-wired logic, and a function modification is enabled by a patch circuit without re-designing of the integrated hard-wired logic controller itself by high-level synthesis even when the function modification... Agent: The University Of Tokyo
20120226891 - Processor with increased efficiency via control word prediction: Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a... Agent: Advanced Micro Devices, Inc.
20120226892 - Method and apparatus for generating efficient code for scout thread to prefetch data values for a main thread: One embodiment of the present invention provides a system that generates code for a scout thread to prefetch data values for a main thread. During operation, the system compiles source code for a program to produce executable code for the program. This compilation process involves performing reuse analysis to identify... Agent:
20120226893 - Hardware controller to choose selected hardware entity and to execute instructions in relation to selected hardware entity: A hardware controller includes a first hardware interface, a second hardware interface, first hardware logic, and second hardware logic. The first hardware interface is to couple the hardware controller to hardware entities of a hardware device in which the hardware controller is to be included. The second hardware interface is... Agent:
20120226894 - Processor, and method of loop count control by processor: The present invention provides a processor comprising: a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued; a data memory that receives, from outside, data that is used for... Agent:Previous industry: Electrical computers and digital processing systems: memory
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