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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) August inventions list 08/12

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
08/30/2012 > 9 patent applications in 8 patent subcategories.

20120221830 - Configurable vector length computer processor: A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more... Agent: Cray Inc.

20120221831 - Accessing common registers in a multi-core processor: Systems and methods for accessing common registers in a multi-core processor are disclosed. In an exemplary embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the... Agent:

20120221832 - Apparatus and methods for in-application programming of flash-based programable logic devices: An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric... Agent:

20120221833 - Integrated circuit with programmable circuitry and an embedded processor system: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The... Agent: Xilinx, Inc.

20120221834 - Processor architecture: A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction;... Agent: Icera Inc

20120221835 - Microprocessor systems and methods for latency tolerance execution: An instruction unit provides instructions for execution by a processor. A decode unit decodes instructions received from the instruction unit. Queues are coupled to receive instructions from the decode unit. Each instruction in a same queue is executed in order by a corresponding execution unit. An arbiter is coupled to... Agent:

20120221836 - Synchronizing commands and dependencies in an asynchronous command queue: Provided are techniques for the managing of command queue dependencies and command queue synchronization. Incoming commands are actively tracked through their dependency relationships. Command dependencies may be tracked across multiple lists, including a submission list and a completion list. Each command on the submission list is prepared for processing and... Agent: International Business Machines Corporation

20120221837 - Running multiply-accumulate instructions for processing vectors: The described embodiments include RunningMAC1P and RunningMAC2P instructions. In the described embodiments, a processor receives a first input vector, a second input vector, a third input vector, and a control vector. Upon executing a RunningMAC1P or a RunningMAC2P instruction, the processor sets a base value equal to a value from... Agent: Apple Inc.

20120221838 - Software programmable hardware state machines: The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the... Agent: Mips Technologies, Inc.

08/23/2012 > 13 patent applications in 11 patent subcategories.

20120216011 - Apparatus and method of single-instruction, multiple-data vector operation masking: An apparatus, method, and medium for performing a vector operation on portions of one or more source vector registers. A vector unit performs an operation on the source vector registers and only stores results in the target vector register for elements which are selected by the vector operation mask. The... Agent:

20120216013 - Efficient and scalable multi-value processor and supporting circuits: Briefly, an efficient and scalable processor device is disclosed that uses multi-value voltages for operands, results, and signaling. An array of cells is arranged in rows and columns, and one or more multi-value operands are used to select a cell from the array. A row driver may be used to... Agent:

20120216012 - Sequential processor comprising an alu array: The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.... Agent: Hyperion Core, Inc.

20120216014 - Applying advanced energy manager in a distributed environment: Techniques are described for abating the negative effects of wait conditions in a distributed system by temporarily decreasing the execution time of processing elements. Embodiments of the invention may generally identify wait conditions from an operator graph and detect the slowest processing element preceding the wait condition based on either... Agent: International Business Machines Corporation

20120216015 - System and method to concurrently execute a plurality of object oriented platform independent programs by utilizing memory accessible by both a processor and a co-processor: The invention achieves efficient execution of programs belonging to an object oriented platform independent language technology like Java, .NET in a multitasking environment by utilizing a processor, a co-processor (executing machine independent instructions) and memory that is accessed by both said processor and said co-processor. The co-processor is agnostic of... Agent:

20120216016 - Instruction scheduling approach to improve processor performance: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at... Agent: International Business Machines Corporation

20120216017 - Parallel computing apparatus and parallel computing method: Computational unit area selecting units, each of which is provided in individual multiple cores, sequentially select uncomputed computational unit areas in a computational area. Computing units, each of which is provided in the individual multiple cores, perform computation for the selected computational unit areas. In addition, the computing units write... Agent: Fujitsu Limited

20120216018 - Processor for performing multiply-add operations on packed data: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said... Agent:

20120216019 - Method of, and apparatus for, stream scheduling in parallel pipelined hardware: There is provided embodiment of methods of generating a hardware design for a pipelined parallel stream processor. An embodiment of the method comprises defining, on a computing device, a processing operation designating processes to be implemented in hardware as part of said pipelined parallel stream processor; defining, on a computing... Agent: Maxeler Technologies, Ltd.

20120216020 - Instruction support for performing stream cipher: Techniques relating to a processor that provides instruction-level support for a stream cipher are disclosed. In one embodiment, the processor supports a first instruction executable to perform an alpha multiplication, an alpha division, and an exclusive-OR operation using a result of the alpha multiplication and a result of the alpha... Agent:

20120216021 - Performing an all-to-all data exchange on a plurality of data buffers by performing swap operations: Methods, apparatus, and products are disclosed for performing an all-to-all exchange on n number of data buffers using XOR swap operations. Each data buffer has n number of data elements. Performing an all-to-all exchange on n number of data buffers using XOR swap operations includes for each rank value of... Agent: International Business Machines Corporation

20120216022 - Controlling the selectively setting of operational parameters for an adapter: An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device... Agent: International Business Machines Corporation

20120216023 - Processor testing: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second... Agent: International Business Machines Corporation

08/16/2012 > 12 patent applications in 11 patent subcategories.

20120210097 - Processor, computational node, parallel computer system, and arithmetic processing method: A management unit causes a plurality of processing units to execute a calculation process. A determining unit determines whether a communication time for a communication process of exchanging a calculation result obtained from the calculation process is longer than a calculation time for the calculation process, the communication process being... Agent: Fujitsu Limited

20120210098 - Enabling virtual calls in a simd environment: Systems and methods of enabling virtual calls in a single instruction multiple data (SIMD) environment may involve detecting a virtual call of a function and using a single dispatch of the function to invoke the virtual call for two or more channels of the virtual call. In one example, it... Agent:

20120210099 - Running unary operation instructions for processing vectors: During operation, a processor generates a result vector. In particular, the processor records a value from an element at a key element position in an input vector into a base value. Next, for each active element in the result vector to the right of the key element position, the processor... Agent: Apple Inc.

20120210100 - Segmental allocation method of expanding risc processor register: A segmental allocation method of expanding RISC processor register includes the steps of a) setting an instruction format of the RISC processor, the destination register field being set having 6 bits to correspond to 64 registers and at least one source register field having at least 4 bits to correspond... Agent:

20120210101 - Competition testing device: A competition testing apparatus for testing an access competition of an arithmetic unit includes a memory that stores a program, a first processor that executes the program by accessing the memory, a second processor that executes the program by accessing the memory, and an arbitration unit that arbitrates accessing the... Agent: Fujitsu Limited

20120210102 - Obtaining and releasing hardware threads without hypervisor involvement: A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to... Agent: International Business Machines Corporation

20120210103 - System and method for multi-core synchronous debugging of a multi-core platform: A system and a corresponding method for multi-core synchronous debugging of a multi-core platform including a plurality of cores are provided. The method includes the following steps. Transmit a core debugging instruction to one of the cores selected by a system debugging instruction or store a group setting included in... Agent: Industrial Technology Research Institute

20120210105 - Processor power consumption control and voltage drop via micro-architectural bandwidth throttling: A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage... Agent:

20120210104 - Suspendable interrupts for processor idle management: Suspendable interrupts are described that allow a processor to remain in an idle state for a longer period of time. Each suspendable interrupt defines a maximum delay value that specifies the maximum delay software associated with the interrupt can wait between a receipt of an interrupt signal associated with the... Agent: Qnx Software Systems Gmbh & Co. Kg

20120210106 - Method of processing instructions in pipeline-based processor: The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according... Agent: International Business Machines Corporation

20120210107 - Predicated issue for conditional branch instructions: A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction, wherein a first path of the branch instruction branches to a target instruction, and wherein a second path of the branch instruction branches to one or more interceding instructions between... Agent: International Business Machines Corporation

20120210108 - Semiconductor device: According to one embodiment, a semiconductor device includes a first sequencer and a second sequencer. The first sequencer operates at a first frequency. The second sequencer operates at a second frequency that is higher than the first frequency. In the first mode, the first sequencer operates in accordance with an... Agent:

08/09/2012 > 17 patent applications in 14 patent subcategories.

20120204001 - Reconfigurable processor and driving control method: Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency,... Agent:

20120204002 - Providing to a parser and processors in a network processor access to an external coprocessor: A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send... Agent: Internaitonal Business Machines Corporation

20120204003 - Invoking multi-library applications on a multiple processor system: A mechanism is provided for invoking multi-library application on a multiple processor system, wherein the multiple processor system comprises a Power Processing Element (PPE) and a plurality of Synergistic Processing Element (SPE). Applications including multi-libraries run in the memory of the PPEs. The mechanism comprises maintaining the status of each... Agent: International Business Machines Corporation

20120204005 - Processor with a coprocessor having early access to not-yet issued instructions: Apparatus and methods provide early access of instructions. A fetch queue is coupled to an instruction cache and configured to store a mix of processor instructions for a first processor and coprocessor instructions for a second processor. A coprocessor instruction selector is coupled to the fetch queue and configured to... Agent: Qualcomm Incorporated

20120204004 - Processor with a hybrid instruction queue: A queuing apparatus having a hierarchy of queues, in one of a number of aspects, is configured to control backpressure between processors in a multiprocessor system. A fetch queue is coupled to an instruction cache and configured to store first instructions for a first processor and second instructions for a... Agent: Qualcomm Incorporated

20120204007 - Controlling the execution of adjacent instructions that are dependent upon a same data condition: A data processing apparatus is disclosed, having: an instruction decoder configured to decode a stream of instructions, a data processor configured to process the decoded stream of instructions; wherein in response to a plurality of adjacent instructions within the stream of instructions execution of which is dependent upon a data... Agent: Arm Limited

20120204006 - Embedded opcode within an intermediate value passed between instructions: A data processing system 2 is used to evaluate a data processing function by executing a sequence of program instructions including an intermediate value generating instruction Inst0 and an intermediate value consuming instruction Inst1. In dependence upon one or more input operands to the evaluation, an embedded opcode within the... Agent: Arm Limited

20120204008 - Processor with a hybrid instruction queue with instruction elaboration between sections: Methods and apparatus for processing instructions by elaboration of instructions prior to issuing the instructions for execution are described. An instruction is received at a hybrid instruction queue comprised of a first queue and a second queue. When the second queue has available space, the instruction is elaborated to expand... Agent: Qualcomm Incorporated

20120204009 - Multi-level register file supporting multiple threads: A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each... Agent: International Business Machines Corporation

20120204010 - Non-quiescing key setting facility: A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of... Agent: International Business Machines Corporation

20120204011 - Asynchronous assist thread initiation: A method of data processing includes a processor of a data processing system executing a controlling thread of a program and detecting occurrence of a particular asynchronous event during execution of the controlling thread of the program. In response to occurrence of the particular asynchronous event during execution of the... Agent: International Business Machines Corporation

20120204012 - Configurable pipeline based on error detection mode in a data processing system: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor... Agent: Rambus Inc.

20120204013 - System and apparatus for group floating-point arithmetic operations: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations... Agent: Microunity Systems Engineering, Inc.

20120204014 - Systems and methods for improving divergent conditional branches: Embodiments of the present invention provide systems, methods, and computer program products for improving divergent conditional branches in code being executed by a processor. For example, in an embodiment, a method comprises detecting a conditional statement of a program being simultaneously executed by a plurality of threads, determining which threads... Agent:

20120204015 - Sharing a data buffer: A computer-program product may have instructions that, when executed, cause a processor to perform operations including managing execution of application functions that access data in a shared buffer; determining if a first instruction that is stored at a first memory location causes, upon execution, data to be read from or... Agent: Apple Inc.

20120204016 - Rewriting branch instructions using branch stubs: Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target... Agent: International Business Machines Corporation

20120204017 - Microprocessor for executing byte compiled java code: The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and... Agent: Atmel Corporation

08/02/2012 > 10 patent applications in 8 patent subcategories.

20120198207 - Asymmetric performance multicore architecture with same instruction set architecture: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating... Agent:

20120198208 - Shared function multi-ported rom apparatus and method: Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit... Agent:

20120198209 - Guest instruction block with near branching and far branching sequence construction to native instruction block: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest far branch, and building an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one... Agent: Soft Machines, Inc.

20120198210 - Microprocessor having novel operations: A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating... Agent:

20120198211 - Arithmetic unit and arithmetic processing method for operating with higher and lower clock frequencies: There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A... Agent: Renesas Electronics Corporation

20120198212 - Microprocessor and method for enhanced precision sum-of-products calculation on a microprocessor: A microprocessor, a method for enhanced precision sum-of-products calculation and a video decoding device are provided, in which at least one general-purpose-register is arranged to provide a number of destination bits to a multiply unit, and a control unit is adapted to provide at least a multiply-high instruction and a... Agent:

20120198214 - N-way memory barrier operation coalescing: One embodiment sets forth a technique for N-way memory barrier operation coalescing. When a first memory barrier is received for a first thread group execution of subsequent memory operations for the first thread group are suspended until the first memory barrier is executed. Subsequent memory barriers for different thread groups... Agent:

20120198213 - Packet handler including plurality of parallel action machines: A packet handler for a packet processing system includes a plurality of parallel action machines, each of the plurality of parallel action machines being configured to perform a respective packet processing function; and a plurality of action machine input registers, wherein each of the plurality of parallel action machines is... Agent: International Business Machines Corporation

20120198215 - Instruction exploitation through loader late fix-up: A method, computer program product, and data processing system for substituting a candidate instruction in application code being loaded during load time. Responsive to identifying the candidate instruction, a determination is made whether a hardware facility of the data processing system is present to execute the candidate instruction. If the... Agent: International Business Machines Corporation

20120198216 - Enhanced monitor facility: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an... Agent: International Business Machines Corporation

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