|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All |
07/2012 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) July category listing 07/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/26/2012 > 14 patent applications in 9 patent subcategories. category listing
20120191945 - Processor architecture with switch matrices for transferring data along buses: There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right... Agent:
20120191946 - Fast remote communication and computation between processors: A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes,... Agent: International Business Machines Corporation
20120191947 - Computer operation control method, program and system: A computer implemented control method, article of manufacture, and computer implemented system for determining whether stack allocation is possible. The method includes: allocating an object created by a method frame to a stack. The allocation is performed in response to: calling a first and second instruction in the method frame;... Agent: International Business Machine Corporation
20120191948 - Nested virtualization performance in a computer system: A virtualization architecture for improving the performance of nested virtualization in a computer system. A virtualization instruction reads or writes data in a control structure used by a virtual machine monitor (VMM) to maintain state on a virtual machine (VM) to support transitions between a root mode of operation of... Agent: International Business Machines Corporation
20120191949 - Predicting a result of a dependency-checking instruction when processing vector instructions: The described embodiments include a processor that executes a vector instruction. In the described embodiments, while dispatching instructions at runtime, the processor encounters a dependency-checking instruction. Upon determining that a result of the dependency-checking instruction is predictable, the processor dispatches a prediction micro-operation associated with the dependency-checking instruction, wherein the... Agent: Apple Inc.
20120191951 - Mfence and lfence micro-architectural implementation method and system: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The... Agent:
20120191950 - Predicting a result for a predicate-generating instruction when processing vector instructions: The described embodiments provide a processor that executes vector instructions. In the described embodiments, while dispatching instructions at runtime, the processor encounters a predicate-generating instruction. Upon determining that a result of the predicate-generating instruction is predictable, the processor dispatches a prediction micro-operation associated with the predicate-generating instruction, wherein the prediction... Agent: Apple Inc.
20120191953 - Parallel execution unit that extracts data parallelism at runtime: Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the... Agent: International Business Machines Corporation
20120191952 - Processor implementing scalar code optimization: Methods and apparatuses are provided for increased efficiency and enhanced power saving in a processor via scalar code optimization. The method comprises determining that an instruction comprises a scalar instruction and then processing the instruction using only a lower portion of an XMM register. The apparatus comprises an operational unit... Agent: Advanced Micro Devices, Inc.
20120191954 - Processor having increased performance and energy saving via instruction pre-completion: Methods and apparatuses are provided for achieving increased performance and energy saving via instruction pre-completion without having to schedule instruction execution in processor execution units. The apparatus comprises an operational unit for determining whether an instruction can be completed without scheduling use of an execution unit of the processor and... Agent: Advanced Micro Devices, Inc.
20120191955 - Method and system for floating point acceleration on fixed point digital signal processors: A system for performing floating point operations comprising a floating point multiply function that utilizes one or more fixed point functional blocks of a processor and one or more dedicated floating point functional blocks of the processor. A floating point add function that utilizes one or more fixed point functional... Agent:
20120191957 - Predicting a result for an actual instruction when processing vector instructions: The described embodiments provide a processor that executes vector instructions. In the described embodiments, while dispatching instructions at runtime, the processor encounters an Actual instruction. Upon determining that a result of the Actual instruction is predictable, the processor dispatches a prediction micro-operation associated with the Actual instruction, wherein the prediction... Agent: Apple Inc.
20120191956 - Processor having increased performance and energy saving via operand remapping: Methods and apparatuses are provided for achieving increased processor performance and energy saving via reordering operand mapping as opposed to the actual operand data. The apparatus comprises a plurality of physical registers available for use storing operands and includes a unit capable of mapping logical registers to the plurality of... Agent: Advanced Micro Devices, Inc.
20120191958 - System and method for context migration across cpu threads: One embodiment of the present invention sets forth a technique for associating arbitrary parallel processing unit (PPU) contexts with a given central processing unit (CPU) thread. The technique introduces two operators used to manage the PPU contexts. The first operator is a PPU context push, which causes a PPU driver... Agent: Nvidia Corporation07/19/2012 > 10 patent applications in 7 patent subcategories. category listing
20120185670 - Scalar integer instructions capable of execution with three registers: A processing core implemented on a semiconductor chip is described. The processing core includes logic circuitry to identify whether vector instructions and integer scalar instructions are to be executed with two registers or three registers, where, in the case of two registers input operand information is destroyed in one of... Agent:
20120185671 - Computational resource pipelining in general purpose graphics processing unit: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for... Agent: Qualcomm Incorporated
20120185672 - Local-only synchronizing operations: Performing a series of successive synchronizing operations by a core on data shared by a plurality of cores may include a first core indicating an upcoming synchronizing operation on shared data. A second memory layer stores the shared data and tracks the first core's ownership of the shared data. The... Agent: International Business Machines Corporation
20120185673 - Reconfigurable processor using power gating, compiler and compiling method thereof: Provided is a reconfigurable processor that may process a first type of operation in first mode using a first group of functional units, and process a second type of operation in second mode using a second group of functional units. The reconfigurable processor may selectively supply power to either the... Agent:
20120185674 - Extending a processor system within an integrated circuit: A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a... Agent: Xilinx, Inc.
20120185675 - Apparatus and method for compressing trace data: An apparatus and method for compressing trace data is provided. The apparatus includes a detection unit configured to detect trace data corresponding to one or more function units performing a substantially significant operation in a reconfigurable processor as valid trace data, and a compression unit configured to compress the valid... Agent: Samsung Electronics Co., Ltd.
20120185676 - Processing apparatus, trace unit and diagnostic apparatus: A processing circuit 4 is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag 22. A trace circuit 6 is provided for generating trace data elements indicative of operations performed by the... Agent: Arm Limited
20120185678 - Hardware thread disable with status indicating safe shared resource condition: A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor... Agent: International Business Machines Corporation
20120185677 - Methods and systems for storage of binary information that is usable in a mixed computing environment: A method of managing binary data across a mixed computing environment is provided. The method includes performing on one or more processors: receiving binary data; receiving binary coded data indicating a type of the binary data; formatting the binary data and the binary coded data according to a first format;... Agent: International Business Machines Corporation
20120185679 - Endpoint-based parallel data processing with non-blocking collective instructions in a parallel active messaging interface of a parallel computer: Endpoint-based parallel data processing with non-blocking collective instructions in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints, each endpoint including a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a... Agent: International Business Machines Corporation07/12/2012 > 6 patent applications in 6 patent subcategories. category listing
20120179893 - Area efficient arrangement of interface devices within an integrated circuit: An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core;... Agent: Arm Limited
20120179894 - Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit: A data processing circuit is described that includes an instruction decoder operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of multiple functional units, and in the second instruction mode instructions controlling only one functional unit. A mode... Agent: Silicon Hive B. V.
20120179895 - Method and apparatus for fast decoding and enhancing execution speed of an instruction: Method and apparatus for fast decoding of microinstructions are disclosed. An integrated circuit is disclosed wherein microinstructions are queued for execution in an execution unit having multiple pipelines where each pipeline is configured to execute a set of supported microinstructions. The execution unit receives microinstruction data including an operation code... Agent: Advanced Micro Devices, Inc.
20120179896 - Method and apparatus for a hierarchical synchronization barrier in a multi-node system: A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality... Agent: International Business Machines Corporation
20120179897 - Techniques for modifying a processor code sequence: A technique of modifying a code sequence for a processor includes identifying a set of one or more target instructions in the code sequence. A replacement instruction is selected that includes a set of replacement instruction parts. A length of each of the replacement instruction parts corresponds to a minimum... Agent:
20120179898 - System and method for enforcing software security through cpu statistics gathered using hardware features: This disclosure is directed to measuring hardware-based statistics, such as the number of instructions executed in a specific section of a program during execution, for enforcing software security. The counting can be accomplished through a specific set of instructions, which can either be implemented in hardware or included in the... Agent: Apple Inc.07/05/2012 > 10 patent applications in 8 patent subcategories. category listing
20120173846 - Method to reduce the energy cost of network-on-chip systems: In a network-on-chip (NoC) system, multiple data messages may be transferred among modules of the system. Power consumption due to the transfer of the messages may affect a cost and overall performance of the system. A described technique provides a way to reduce a volume of data transferred in the... Agent: Stmicroelectronics (beijing) R&d Co., Ltd.
20120173847 - Parallel processor and method for thread processing thereof: A parallel processor and a method for concurrently processing threads in the parallel processor are disclosed. The parallel processor comprises: a plurality of thread processing engines for processing threads distributed to the thread processing engines, and the plurality of thread processing engines being connected in parallel; a thread management unit... Agent:
20120173849 - Methods and apparatus for scalable array processor interrupt detection and response: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When... Agent: Altera Corporation
20120173848 - Pipeline flush for processor that may execute instructions out of order: An embodiment of an instruction pipeline includes first and second sections. The first section is operable to provide first and second ordered instructions, and the second section is operable, in response to the second instruction, to read first data from a data-storage location, is operable, in response to the first... Agent: Stmicroelectronics R&d (beijing) Co. Ltd
20120173850 - Information processing apparatus: A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means... Agent: Renesas Electronics Corporation
20120173851 - Mechanism for maintaining dynamic register-level memory-mode flags in a virtual machine system: A method for maintaining dynamic register-level memory-mode flags in a virtual machine includes parsing a machine instruction of a live memory analysis command in a virtual machine (VM). The machine instruction can include an instruction opcode, a source address referring to a first type of memory and a destination address... Agent: International Business Machines Corporation
20120173852 - Instruction set extension using 3-byte escape opcode: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the... Agent:
20120173853 - Processing apparatus and method for performing computation: A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data... Agent: Fujitsu Limited
20120173854 - Processor having increased effective physical file size via register mapping: Methods and apparatuses are provided for an efficient technique for processing registers having a known value while improving processor performance. The apparatus comprises a processor having a plurality of physical registers available for use in computations and a decoder for determining that a logical register contains a known value. A... Agent: Advanced Micro Devices, Inc.
20120173855 - Exception transporting and handling of concurrent exceptions: Methods and systems for handling exceptions, including being provided with a catch list, the catch list being a flattened inheritance tree for exception types in ascending inheritance order, receiving an exception from a thread, searching the catch list in ascending inheritance order to find a matching exception type to received... Agent: Zebra Imaging, Inc.Previous industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.