|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) June invention type 06/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 06/28/2012 > 17 patent applications in 15 patent subcategories.
20120166761 - Vector conflict instructions: A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second... Agent:
20120166762 - Computing apparatus and method based on a reconfigurable single instruction multiple data (simd) architecture: Provided are a computing apparatus and method based on SIMD architecture capable of supporting various SIMD widths without wasting resources. The computing apparatus includes a plurality of configurable execution cores (CECs) that have a plurality of execution modes, and a controller for detecting a loop region from a program, determining... Agent:
20120166763 - Dynamic multi-core microprocessor configuration discovery: A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the microprocessor's cores. Upon reset, the microcode queries and/or receives from other cores configuration-revealing information and collects the configuration-revealing information to determine a... Agent: Via Technologies, Inc.
20120166764 - Dynamic and selective core disablement and reconfiguration in a multi-core processor: Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is... Agent: Via Technologies, Inc.
20120166765 - Predicting branches for vector partitioning loops when processing vector instructions: While fetching the instructions from a loop in program code, a processor calculates a number of times that a backward-branching instruction at the end of the loop will actually be taken when the fetched instructions are executed. Upon determining that the backward-branching instruction has been predicted taken more than the... Agent: Apple Inc.
20120166766 - Enhanced microcode address stack pointer manipulation: Methods and apparatus for enhanced microcode address stack pointer manipulation are described. In one embodiment, the stacks are invisible to software. In an embodiment, a microcode instruction pointer (UIP) and a next address to be accessed in a microcode storage unit are generated based on an opcode of a microoperation,... Agent:
20120166767 - System, apparatus, and method for segment register read and write regardless of privilege level: Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic... Agent:
20120166768 - Pipeline replay support for multicycle operations: Instructions asserted in the instruction pipeline of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with... Agent:
20120166770 - Instruction execution: A method of executing an instruction set including a first instruction and a second instruction, includes reading the first instruction; determining whether the first instruction is an instruction which is integral with the second instruction; reading the second instruction; if the first instruction is integral with the second instruction, interpreting... Agent: Cambridge Silicon Radio Limited
20120166769 - Processor having increased performance via elimination of serial dependencies: Methods and apparatuses are provided for achieving increased performance via elimination of serial dependencies in instructions or instruction sequences. The apparatus comprises an operational unit for determining whether an instruction will cause dependencies during completion in an execution unit. Responsive to that determination the instruction is replaced with an alternative... Agent: Advanced Micro Devices, Inc.
20120166771 - Agile communication operator: A high level programming language provides an agile communication operator that generates a segmented computational space based on a resource map for distributing the computational space across compute nodes. The agile communication operator decomposes the computational space into segments, causes the segments to be assigned to compute nodes, and allows... Agent: Microsoft Corporation
20120166772 - Extensible data parallel semantics: A high level programming language provides extensible data parallel semantics. User code specifies hardware and software resources for executing data parallel code using a compute device object and a resource view object. The user code uses the objects and semantic metadata to allow execution by new and/or updated types of... Agent: Microsoft Corporation
20120166773 - Hash processing using a processor: In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance with the SHA-1 standard, where M includes N blocks M(i), i=1, . . . , N, and... Agent: Lsi Corporation
20120166774 - Computer-readable medium storing processor testing program: A non-transitory computer-readable medium storing a processor testing program causing a computer to execute a testing process for a processor, the processor having a plurality of pipeline stages for processing an instruction and a controller for providing the pipeline stage with an inter-lock signal for aborting a transition of the... Agent: Fujitsu Semiconductor Limited
20120166775 - Combined level 1 and level 2 branch predictor: A branch predictor for use in a processor includes a Level 1 branch predictor, a Level 2 branch predictor, a match determining circuit, and an override determining circuit. The Level 1 branch predictor generates a Level 1 branch prediction. The Level 2 branch predictor generates a Level 2 branch prediction.... Agent: Advanced Micro Devices, Inc.
20120166776 - Method, system, and computer program for analyzing program: Upon start of a program, a plurality of flags, each corresponding to an instruction of the program, are initialized to a disabled state and an initial state of a BHT is stored. Upon execution of a branch instruction, if a branch has not been taken, a value of history information... Agent: International Business Machines Corporation
20120166777 - Method and apparatus for switching threads: Techniques for switching or parking threads in a processor including a plurality of processor cores that share a microcode engine are disclosed. In a dual-core or multi-core system, a front end, (e.g., microcode engine), of the processor cores may be shared by the two or more active threads in order... Agent: Advanced Micro Devices, Inc.06/21/2012 > 17 patent applications in 13 patent subcategories.
20120159118 - Lower ic package structure for coupling with an upper ic package to form a package-on-package (pop) assembly and pop assembly including such a lower ic package structure: Disclosed are embodiments of a lower integrated circuit (IC) package structure for a package-on-package (PoP) assembly. The lower IC package structure includes an interposer having pads to mate with terminals of an upper IC package. An encapsulant material is disposed in the lower IC package, and this encapsulant may be... Agent:
20120159119 - System and methodology for development of a system architecture: Described embodiments relate to methods, systems and computer readable medium for developing a system architecture. Resources constraints are defined, where each resource constraint corresponds to a maximum number of a each kind of resources available to construct the system architecture. Constraint values for each of at least three optimization parameters... Agent:
20120159120 - Method and apparatus for scheduling the issue of instructions in a microprocessor using multiple phases of execution: A microprocessor configured to execute programs divided into discrete phases, comprising: a scheduler for scheduling program instructions to be executed on the processor; a plurality of resources for executing programming instructions issued by the scheduler; wherein the scheduler is configured to schedule each phase of the program only after receiving... Agent:
20120159121 - Parallel computer system, synchronization apparatus, and control method for the parallel computer system: A synchronization apparatus includes a receiver that receives data from a synchronization apparatus of another node that performs synchronization with its own node from among the plurality of synchronization apparatuses and extracts synchronization information from the received data, a transmitter that transmits the data to the synchronization apparatus of the... Agent: Fujitsu Limited
20120159122 - Systems and methods for lattice reduction: Disclosed herein are lattice reduction systems and methods for a MIMO communication system. One such method includes providing a channel matrix corresponding to a channel in a MIMO communication system, preprocessing the channel matrix to form at least an upper triangular matrix, implementing a relaxed size reduction process, and implementing... Agent: Georgia Tech Research Corporation
20120159123 - Cstate boost method and apparatus: A central processing unit (processor) having multiple cores and a method for controlling the performance of the processor. The processor includes a first storage location configured to store a first threshold associated with a first boost performance state (P-State). The processor also includes logic circuitry configured to increase performance of... Agent: Advanced Micro Devices, Inc.
20120159125 - Efficiency of short loop instruction fetch: A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short... Agent: International Business Machines Corporation
20120159124 - Method and system for computational acceleration of seismic data processing: A computer-implemented method and a system for computational acceleration of seismic data processing are described. The method includes defining a specific non-uniform memory access (NUMA) scheduling for a plurality of cores in a processor according to data to be processed; and running two or more threads through each of the... Agent: Chevron U.s.a. Inc.
20120159126 - Programming language exposing idiom calls: A programming language may include hint instructions that may notify a programming idiom accelerator that a programming idiom is coming. An idiom begin hint exposes the programming idiom to the programming idiom accelerator. Thus, the programming idiom accelerator need not perform pattern matching or other forms of analysis to recognize... Agent:
20120159127 - Security sandbox: Different instruction sets are provided for different units of execution such as threads, processes, and execution contexts. Execution units may be associated with instruction sets. The instruction sets may have mutually exclusive opcodes, meaning an opcode in one instruction set is not included in any other instruction set. When executing... Agent: Microsoft Corporation
20120159128 - Handling media streams in a programmable bit processor: In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the... Agent:
20120159129 - Programmable logic array and read-only memory area reduction using context-sensitive logic for data space manipulation: A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form.... Agent:
20120159130 - Mechanism for conflict detection using simd: A system and method are configured to detect conflicts when converting scalar processes to parallel processes (“SIMDifying”). Conflicts may be detected for an unordered single index, an ordered single index and/or ordered pairs of indices. Conflicts may be further detected for read-after-write dependencies. Conflict detection is configured to identify operations... Agent:
20120159131 - System and method for performing deterministic processing: A system and method is provided for performing deterministic processing on a non-deterministic computer system. In one example, the system forces execution of one or more computer instructions to execute within a constant execution time. A deterministic engine, if necessary, waits a variable amount of time to ensure that the... Agent: Bin1 Ate LLC
20120159132 - Accelerating data packet parsing: Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in... Agent: International Business Machines Corporation
20120159133 - Business exception management pattern for business processes: Handling business process exceptions. A method includes a computing system using a template, causing one or more operations to be performed to determine a problem that caused a business process exception. The computing system uses a template to cause one or more operations to be performed to perform one or... Agent: Microsoft Corporation
20120159134 - Exception control method, system, and program: A method for programmably controlling an exception includes performing, by a processor, a step of executing a control specification instruction for exception control specification that indicates whether an exception is enabled or not and setting a control specification value for the exception in a register and a step of executing... Agent: International Business Machines Corporation06/14/2012 > 13 patent applications in 9 patent subcategories.
20120151182 - Performing function calls using single instruction multiple data (simd) registers: In one embodiment, a processor can perform a function call from a main program to a function that is to operate on at least one vector-type operand, in which only scalar values are passed to the function, and input values to the function including the at least one vector-type operand... Agent:
20120151183 - Enhancing performance by instruction interleaving and/or concurrent processing of multiple buffers: An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The... Agent:
20120151184 - Hard object: constraining control flow and providing lightweight kernel crossings: A method providing simple fine-grain hardware primitives with which software engineers can efficiently implement enforceable separation of programs into modules and constraints on control flow, thereby providing fine-grain locality of causality to the world of software. Additionally, a mechanism is provided to mark some modules, or parts thereof, as having... Agent:
20120151186 - Controlling simulation of a microprocessor instruction fetch unit through manipulation of instruction addresses: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be... Agent: International Business Machines Corporation
20120151185 - Fine-grained privilege escalation: A processor and a method for privilege escalation in a processor are provided. The method may comprise fetching an instruction from a fetch address, where the instruction requires the processor to be in supervisor mode for execution, and determining whether the fetch address is within a predetermined address range. The... Agent: International Business Machines Corporation
20120151190 - Data processing apparatus, data processing method, and non-transitory computer readable storage medium: A data processing apparatus includes an output unit. The output unit determines, when parallel control is performed in a data processor created in the data processing apparatus so that plural processing modules forming the data processor perform data processing in parallel, on the basis of a value representing a parallel-processing... Agent: Fuji Xerox Co., Ltd.
20120151189 - Data processing with variable operand size: A method of processing data comprising performing a sequence of operation instructions with variable operand size, wherein respective size codes for different source and destination operands are obtained and registered separately from performing the sequence of operation instructions, and the sequence of operation instructions is performed using operand sizes defined... Agent: Freescale Semiconductor, Inc.
20120151187 - Instruction optimization: Programs can be optimized at runtime prior to execution to enhance performance. Program instructions/operations designated for execution can be recorded and subsequently optimized at runtime prior to execution, for instance by performing transformations on the instructions. For example, such optimization can remove, reorder, and/or combine instructions, among other things.... Agent: Microsoft Corporation
20120151188 - Type and length abstraction for data types: Embodiments are directed to implementing a generic SIMD data type in software code. In an embodiment, a computer system accesses a portion of software code that includes an algorithm with a generic SIMD data type that includes a variable number of elements. The algorithm with the generic SIMD data type... Agent: Microsoft Corporation
20120151191 - Reducing power consumption in multi-precision floating point multipliers: Methods and apparatus relating to reducing power consumption in multi-precision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in response to two or more multiplication operations with the same data size and data type occurring back-to-back. Other embodiments are also claimed and described.... Agent:
20120151192 - Very long instruction word (vliw) processor with power management, and apparatus and method of power management therefor: A very long instruction word (VLIW) processor and an apparatus with power management and a method of power management therefor are provided in consistent with the exemplary embodiments of the disclosure. The power management method includes the following steps. Valid instruction(s) and no operation (NOP) instruction(s) of an input instruction... Agent: Industrial Technology Research Institute
20120151193 - Optimized buffer placement based on timing and capacitance assertions: A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source... Agent: International Business Machines Corporation
20120151194 - Bytecode branch processor and method: A bytecode interpreter in a computing system is provided. The interpreter assists in branch prediction by a host processor that processes a virtual machine such as JAVA® and DALVIK®, thereby reducing branch misprediction and achieving high performance.... Agent:06/07/2012 > 21 patent applications in 18 patent subcategories.
20120144155 - System of rotating data in a plurality of processing elements: A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to... Agent: Micron Technology, Inc.
20120144156 - Method for controlling information processing apparatus and information processing apparatus: A method for controlling an information processing apparatus including a processor which operates an operating system and a kernel which is operated independently of the operating system, and a network interface through which the information processing apparatus is connectable to an other information processing apparatus, the method includes notifying, by... Agent: Fujitsu Limited
20120144157 - Allocation of mainframe computing resources using distributed computing: There is disclosed a system and method for allocation of mainframe computing resources using distributed computing. In particular, the present application is directed to a system whereby a mainframe process intended for execution on a metered processor may be identified as executable on a non-metered processor. Thereafter, the mainframe computer... Agent:
20120144158 - Systems and methods for compiling an application for a parallel-processing computer system: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance... Agent:
20120144159 - Quantum processor: One embodiment of the invention includes a quantum processor system. The quantum processor system includes a first resonator having a first characteristic frequency and a second resonator having a second characteristic frequency greater than the first characteristic frequency. A qubit cell is coupled to each of the first resonator and... Agent: Northrop Grumman Systems Corporation
20120144160 - Multiple-cycle programmable processor: The multi-cycle programmable processor emulates the features of a conventional microprocessor. Processor hardware functional units include a program counter (instruction pointer), an arithmetic and logic unit, an accumulator, an instruction register, a 2×1 multiplexer, 2×4 decoder, 1×2 decoder, an AND gate and an OR gate. Additionally, a controller modeled by... Agent: King Fahd University Of Petroleum And Minerals
20120144161 - Carryless multiplication preformatting apparatus and method: An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless multiplication instruction, and is configured to assert a carryless signal responsive to receipt of the carryless multiplication instruction. The carryless preformat unit... Agent: Via Technologies, Inc.
20120144162 - Systems and methods for determining compute kernels for an application in a parallel-processing computer system: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance... Agent:
20120144163 - Data processing method and system based on pipeline: A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index,... Agent: International Business Machines Corporation
20120144164 - Processor register recovery after flush operation: An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction... Agent: International Business Machines Corporation
20120144166 - Control signal memoization in a multiple instruction issue microprocessor: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register... Agent: International Business Machines Corporation
20120144165 - Sideband payloads in pseudo no-operation instructions: A pseudo no-op instruction in an instruction stream is detected, and the pseudo no-op instruction is decoded as being an opcode, wherein a parameter of the pseudo no-op instruction uniquely identifies the opcode. The method makes use of a pseudo no-op instruction and provides the pseudo no-op instruction with additional... Agent: International Business Machines Corporation
20120144167 - Apparatus for executing programs for a first computer architecture on a computer of a second architecture: A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA.... Agent: Ati Technologies Ulc
20120144169 - Information processing apparatus, information processing method, and computer readable medium: An information processing apparatus includes the following elements. A generator generates, on the basis of instruction information which describes processing to be executed for obtaining output data from raw data, processing definition information that defines details of the processing, upon inputting the instruction information. A determination unit determines whether output... Agent: Fuji Xerox Co., Ltd.
20120144168 - Odd and even start bit vectors: A method and apparatus is presented for identifying instructions in a stream of information by preprocessing the stream of information, creating a vector of instructions and breaking the vector of instructions into two or more vectors for picking the identified instructions at a high frequency.... Agent: Advanced Micro Devices, Inc.
20120144170 - Dynamically scalable per-cpu counters: Embodiments include a reference counting system and method for a multiprocessor system including distributed per-CPU counters having a dynamically variable batch size. A global counter is dynamically updated as each per-CPU counter reaches its associated batch size. An initial batch size provides a desired scalability. The batch size is automatically... Agent: International Business Machines Corporation
20120144171 - Mechanism for detection and measurement of hardware-based processor latency: A mechanism for detection and measurement of hardware-based processor latency is disclosed. A method of the invention includes issuing an instruction to stop all running instructions on one or more processors of a multi-core computing device, starting a latency measurement code loop on each of the one or more processors,... Agent:
20120144172 - Interrupt distribution scheme: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in... Agent:
20120144173 - Unified scheduler for a processor multi-pipeline execution unit and methods: A unified scheduler for a processor execution unit and methods are disclosed for providing faster throughput of micro-instruction/operation execution with respect to a multi-pipeline processor execution unit. In one example, an execution unit has a plurality of pipelines that operate at a predetermined clock rate, each pipeline configured to process... Agent: Advanced Micro Devices, Inc.
20120144175 - Method and apparatus for an enhanced speed unified scheduler utilizing optypes for compact logic: An integrated circuit is disclosed wherein microinstructions are selectively queued for execution in an execution unit having multiple pipelines where each pipeline is configured to execute a selected subset of a set of supported microinstructions. The execution unit receives microinstruction data including an operation code OpCode and an operation type... Agent: Advanced Micro Devices, Inc.
20120144174 - Multiflow method and apparatus for operation fusion: A method and apparatus for utilizing scheduling resources in a processor are disclosed. A complex operation is assigned for execution as two micro-operations; a first micro-operation and a second micro-operation. The first micro-operation, which may be an address-generation operation, is executed using at least one of a first processing unit... Agent: Advanced Micro Devices, Inc.Previous industry: Electrical computers and digital processing systems: memory
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