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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) May archived by USPTO category 05/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/31/2012 > 4 patent applications in 4 patent subcategories. archived by USPTO category
20120137108 - Systems and methods integrating boolean processing and memory: The present disclosure relates to placing a Boolean Processor on a chip with memory to eliminate memory latency issues in computing systems. An asynchronous implementation of a Boolean Processor Switched Memory can theoretically operate at terahertz speed and vastly improve the rate at which computationally relevant data is fed to... Agent:
20120137109 - Method and apparatus for performing store-to-load forwarding from an interlocking store using an enhanced load/store unit in a processor: A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of... Agent: Advanced Micro Devices, Inc.
20120137110 - Hardware device for processing the tasks of an algorithm in parallel: A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source... Agent: International Business Machines Corporation
20120137111 - Loop detection apparatus, loop detection method, and loop detection program: A loop detection method, system, and article of manufacture for determining whether a sequence of unit processes continuously executed among unit processes in a program is a loop by means of computational processing performed by a computer. The method includes: reading address information on the sequence of unit processes; comparing... Agent: International Business Machines Corporation05/24/2012 > 9 patent applications in 8 patent subcategories. archived by USPTO category
20120131308 - System, device, and method for on-the-fly permutations of vector memories for executing intra-vector operations: A device system and method for processing program instructions, for example, to execute intra vector operations. A fetch unit may receive a program instruction defining different operations on data elements stored at the same vector memory address. A processor may include different types of execution units each executing a different... Agent:
20120131309 - High-performance, scalable mutlicore hardware and software system: Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system in provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and... Agent: Texas Instruments Incorporated
20120131310 - Methods and apparatus for independent processor node operations in a simd array processor: A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pause its instruction fetching. A local PE instruction memory (PE Imem)... Agent: Altera Corporation
20120131311 - Correlation-based instruction prefetching: The disclosed embodiments provide a system that facilitates prefetching an instruction cache line in a processor. During execution of the processor, the system performs a current instruction cache access which is directed to a current cache line. If the current instruction cache access causes a cache miss or is a... Agent: Oracle International Corporation
20120131312 - Data processing apparatus and method: A data processing apparatus 2 comprises a processing circuit 4 and instruction decoder 6. A bitfield manipulation instruction controls the processing apparatus 2 to generate at least one result data element from corresponding first and second source data elements src1, src2. Each result data element includes a portion corresponding to... Agent: Arm Limited
20120131313 - Error recovery following speculative execution with an instruction processing pipeline: An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be... Agent: Arm Limited
20120131315 - Data processing apparatus: A data processing apparatus may include a processing unit that performs processing related to data, a first register that holds a value for defining an operation of the processing unit, a second register that holds a value output from the first register, the second register outputting the value to the... Agent: Olympus Corporation
20120131314 - Ganged hardware counters for coordinated rollover and reset operations: Mechanisms for controlling rollover or reset of hardware performance counters in the data processing system. A signal indicating that a rollover or reset of a first hardware performance counter has occurred is received and it is determined if the first hardware performance counter is analytically related to one or more... Agent: International Business Machines Corporation
20120131316 - Method and apparatus for improved secure computing and communications: A method and apparatus are disclosed that may comprise applying compact markup notation to a general recursive computing system including hardware and software components, the compact markup notation defining things, places, paths, actions and causes within at least one of the hardware and the software of the general recursive computing... Agent:05/17/2012 > 20 patent applications in 16 patent subcategories. archived by USPTO category
20120124332 - Vector processing circuit, command issuance control method, and processor system: A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts... Agent: Fujitsu Limited
20120124333 - Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures,... Agent: Qst Holdings LLC
20120124334 - Simd processor for performing data filtering and/or interpolation: Data processing circuit containing an instruction execution circuit having an instruction set comprising a SIMD instruction. The instruction execution circuit comprises arithmetic circuits, arranged to perform N respective identical operations in parallel in response to the SIMD instruction. The SIMD instruction selects a first one and a second one of... Agent: Silicon Hive B. V.
20120124335 - System core for transferring data between an external device and memory: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the... Agent: Altera Corporation
20120124336 - Signal processing system and integrated circuit comprising a prefetch module and method therefor: A signal processing system comprising at least one master device at least one memory element and prefetch module arranged to perform prefetching from at least one memory element upon a memory access request to the at least one memory element from the at least one master device. Upon receiving a... Agent: Freescale Semiconductor, Inc.
20120124337 - Size mis-match hazard detection: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the... Agent: Arm Limited
20120124338 - Multi-threaded data processing system: A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads (32, 34) with differing hardware resources comprising the steps of receiving a plurality of streams of instructions (38, 44) and determining which hardware threads are able to receive instructions for execution (40, 46),... Agent:
20120124339 - Processor core selection based at least in part upon at least one inter-dependency: An embodiment may include at least one first process to be executed, at least in part, by circuitry. The at least one first process may select, at least in part, from a plurality of processor cores, one or more processor cores to execute, at least in part, at least one... Agent:
20120124340 - Retirement serialisation of status register access operations: A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits... Agent: Arm Limited
20120124341 - Methods and apparatus for performing multiple operand logical operations in a single instruction: A method for performing multiple-operand logical operations in a single instruction includes the steps of: generating a table defining a correspondence between a plurality of input variables to a multiple-operand logical operation and a plurality of output results of the multiple-operand logical operation; encoding the table to generate a set... Agent:
20120124343 - Apparatus and method for modifying instruction operand: Provided are an apparatus and method for modifying an instruction operand. The apparatus includes a first selector configured to receive first instruction operands and a second selector configured to receive second instruction operands. The apparatus also includes a modification unit configured to select a first instruction operand and a second... Agent:
20120124342 - Concurrent core affinity for weak cooperative multithreading systems: A data structure is stored. Further, a plurality of operations performed on the data structure is modified to be per core instead of per thread so that a subset of the plurality of threads safely share the data structure. In addition, interruption of each of the plurality of threads in... Agent: International Business Machines Corporation
20120124344 - Loop predictor and method for instruction fetching using a loop predictor: A loop predictor and a method for instruction fetching using a loop predictor. A processor may include a loop predictor in addition to a primary branch predictor. A relatively common scenario in program execution is that a set of branches repeat over and over forming a loop. The loop may... Agent: Advanced Micro Devices, Inc.
20120124345 - Cumulative confidence fetch throttling: A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.... Agent:
20120124347 - Branch prediction scheme utilizing partial-sized targets: A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a... Agent:
20120124346 - Decoding conditional program instructions: A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation... Agent: Arm Limited
20120124348 - Branch predictor accuracy by forwarding table updates to pending branch predictions: A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an instruction being speculatively executed a first time; and provides a second instance of the branch prediction value associated with the... Agent:
20120124349 - Power efficient pattern history table fetch in branch predictor: A method and apparatus for branch prediction is disclosed. A pattern history table (PHT) is accessed based on at least one global history value to obtain a prediction value. The prediction value and the at least one global history value used to obtain the prediction value are placed in a... Agent: Advanced Micro Devices, Inc.
20120124351 - Apparatus and method for dynamically determining execution mode of reconfigurable array: An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction... Agent:
20120124350 - Table-driven soaker tool for information handling systems: A soaker tool for an information handling system (IHS) exercises the IHS to provide a predetermined amount of utilization that a user may specify. The soaker tool schedules wait times following respective utilization times in alternating fashion to achieve a desired utilization value for a predetermined time period. The soaker... Agent: International Business Machines Corporation05/10/2012 > 6 patent applications in 6 patent subcategories. archived by USPTO category
20120117357 - Energy tile processor: An energy tile processor in which an internal structure of a single processor is divided into a part for supplying instructions and another part for executing the instructions in order for operating voltages and operating frequencies to be supplied independently. The processor includes an instruction supply unit storing instructions and... Agent: Electronics And Telecommunications Research Institute
20120117358 - Software selectable adjustment of simd parallelism: Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a software instruction of the program sets a... Agent: Qualcomm Incorporated
20120117359 - No-delay microsequencer: An apparatus generally including a memory and a circuit is disclosed. The memory may be configured to store a plurality of instructions. Each of the instructions generally includes a corresponding command and a corresponding command repeat count. At least one of the instructions may include a subprocedure call. The circuit... Agent:
20120117360 - Dedicated instructions for variable length code insertion by a digital signal processor (dsp): In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The... Agent: Texas Instruments Incorporated
20120117361 - Processing data communications events in a parallel active messaging interface of a parallel computer: Processing data communications events in a parallel active messaging interface (‘PAMI’) of a parallel computer that includes compute nodes that execute a parallel application, with the PAMI including data communications endpoints, and the endpoints are coupled for data communications through the PAMI and through other data communications resources, including determining... Agent: International Business Machines Corporation
20120117362 - Replay of detected patterns in predicted instructions: Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to predict a sequence of instructions to be issued by the processor for execution. The processor also includes a pattern detection unit configured... Agent:05/03/2012 > 9 patent applications in 8 patent subcategories. archived by USPTO category
20120110302 - Accelerating generic loop iterators using speculative execution: A method, a system and a computer program product for effectively accelerating loop iterators using speculative execution of iterators. An Efficient Loop Iterator (ELI) utility detects initiation of a target program and initiates/spawns a speculative iterator thread at the start of the basic code block ahead of the code block... Agent: Ibm Corporation
20120110303 - Method for process synchronization of embedded applications in multi-core systems: A system and method for process synchronization in a multi-core computer system. A separate non-caching memory enables a method to synchronize processes executing on multiple processor cores. Since only a very small amount (a few number of bytes), is needed for the synchronization, it is possible to extend the method... Agent: International Business Machines Corporation
20120110304 - Pipelined serial ring bus: The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with... Agent:
20120110305 - Register renamer that handles multiple register sizes aliased to the same storage locations: A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such... Agent:
20120110306 - Translated memory protection apparatus for an advanced microprocessor: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction,... Agent:
20120110307 - Compressed instruction processing device and compressed instruction generation device: A compressed instruction processing device has: a compressed instruction expanding circuit which expands a compressed instruction code that include a difference code between an instruction code being a compression object and a reference instruction code and which outputs an expanded instruction code; an instruction buffer storing the instruction code expanded... Agent: Fujitsu Semiconductor Limited
20120110308 - Method for controlling bmc having customized sdr: A Baseboard Management Controller (BMC) controlling method includes the steps of dividing a memory of a BMC into an original region and customized region, in which the original region includes at least one original sensor data record (SDR) and original platform event filter (PEF) corresponding to each other; providing an... Agent: Inventec Corporation
20120110309 - Data output transfer to memory: Methods, systems, and computer readable media for improved transfer of processing data outputs to memory are disclosed. According to an embodiment, a method for transferring outputs of a plurality of threads concurrently executing in one or more processing units to a memory includes: forming, based upon one or more of... Agent: Ati Technologies Ulc
20120110310 - Microprocessor with pipeline bubble detection device: A microprocessor includes a pipeline microarchitecture and a pipeline bubble detection device. The pipeline bubble detection device has a minimum execution clock cycle ascertainment unit for ascertaining a minimum or optimum number of execution clock cycles for one or more program commands which pass through the pipeline microarchitecture or are... Agent:Previous industry: Electrical computers and digital processing systems: memory
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