|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) April category listing, related patent applications 04/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/26/2012 > 5 patent applications in 5 patent subcategories.
20120102299 - Stall propagation in a processing system with interspersed processors and communicaton elements: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output... Agent:
20120102300 - Asynchronous pipeline system, stage, and data transfer mechanism: Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first... Agent: Electronics And Telecommunications Research Institute
20120102301 - Predicate count and segment count instructions for processing vectors: The described embodiments comprise a PredCount instruction and a SegCount instruction. When executed by a processor, the PredCount instruction causes the processor to analyze a predicate vector to determine a number of active elements in the predicate vector that exhibit a predetermined condition (e.g., that are set to a predetermined... Agent: Apple Inc.
20120102302 - Processor testing: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second... Agent: International Business Machines Corporation
20120102303 - Exception control in a multiprocessor system: A data processing apparatus is provided with a plurality of processing units (4 to 18; 32 to 38) executing respective streams of program instructions corresponding to respective processing threads. Exception control circuitry 20, 42 controls exception processing for a group of the processing unit in response to an exception triggering... Agent: Arm Limited04/19/2012 > 10 patent applications in 8 patent subcategories.
20120096238 - Circuit and method for parallel perforation in speed rate matching: The present invention discloses a circuit and a method for parallel perforation in rate matching, which can reduce the perforation processing time delay to satisfy the requirements of a Long Term Evolution (LTE). Both the circuit and the method can adopt three selector arrays and three register groups. Specifically, the... Agent: Zte Corporation
20120096239 - Low power execution of a multithreaded program: Technologies for low power execution of one or more threads of a multithreaded program by one or more processing elements are generally disclosed.... Agent: Empire Technology Development LLC
20120096240 - Application performance with support for re-initiating unconfirmed software-initiated threads in hardware: A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be... Agent: International Business Machines Corporation
20120096241 - Performance of emerging applications in a virtualized environment using transient instruction streams: A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction... Agent: International Business Machines Corporation
20120096242 - Method and apparatus for performing control of flow in a graphics processor architecture: Methods and systems for performing control of flow in a graphics processor architecture are provided. For example, in at least one embodiment, a computing system includes a memory storing a plurality of instructions and a graphics processing unit. The graphics processing unit is configured to process the instructions according to... Agent: Via Technologies, Inc.
20120096243 - Multithreaded processor with multiple concurrent pipelines per thread: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective... Agent: Aspen Acquisition Corporation
20120096244 - Method, system, and product for performing uniformly fine-grain data parallel computing: A method is disclosed that includes computing, using at least one uniformly fine-grain data parallel computing unit, a mean-square error regression within a regression clustering algorithm. The mean-square error regression is represented in the form of at least one summation of a vector-vector multiplication. A computer program product and a... Agent:
20120096245 - Computing device, parallel computer system, and method of controlling computer device: A computing device includes a receiving unit that receives control information indicating an instruction to be executed on a process that is distributed or an instruction contained in the process that is distributed, from a control information creating device that transmits the control information to each computing device on a... Agent: Fujitsu Limited
20120096246 - Nonvolatile storage using low latency and high latency memory: Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of a data block is stored in the phase change memory and a second portion of the data block is stored in the FLASH memory. The first... Agent:
20120096247 - Reconfigurable processor and method for processing loop having memory dependency: Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the... Agent:04/12/2012 > 13 patent applications in 11 patent subcategories.
20120089812 - Shared resource multi-thread processor array: A shared resource multi-thread processor array wherein an array of heterogeneous function blocks are interconnected via a self-routing switch fabric, in which the individual function blocks have an associated switch port address. Each switch output port comprises a FIFO style memory that implements a plurality of separate queues. Thread queue... Agent:
20120089813 - Computing apparatus based on reconfigurable architecture and memory dependence correction method thereof: Provided are a computing apparatus based on a reconfigurable architecture and a memory dependence correction method thereof. In one general aspect, a computing apparatus has a reconfigurable architecture. The computing apparatus may include: a reconfiguration unit having processing elements configured to reconfigure data paths between one or more of the... Agent:
20120089814 - Inter-processor protocol in a multi-processor system: In a multiprocessor system, a primary processor may store an executable image for a secondary processor. A communication protocol assists the transfer of an image header and data segment(s) of the executable image from the primary processor to the secondary processor. Messages between the primary processor and secondary processor indicate... Agent: Qualcomm Incorporated
20120089815 - Determining processor offsets to synchronize processor time values: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A... Agent: International Business Machines Corporation
20120089816 - Query sampling information instruction: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data... Agent: International Business Machines Corporation
20120089817 - Conditional selection of data elements: A data processing apparatus, method and computer program that perform an operation on one data element such as a register and then conditionally select either that register or a further register on which no operation has been performed. The apparatus comprises an instruction decoder configured to decode at least one... Agent:
20120089818 - Decoding instructions from multiple instructions sets: A data processing apparatus, method and computer program are described that are capable of decoding instructions from different instruction sets. The method comprising: receiving an instruction; if an operation code of said instruction is an operation code of an instruction from a base set of instructions decoding said instruction according... Agent: Arm Limited
20120089819 - Issuing instructions with unresolved data dependencies: The described embodiments include a processor that determines instructions that can be issued based on unresolved data dependencies. In an issue unit in the processor, the processor keeps a record of each instruction that is directly or indirectly dependent on a base instruction. Upon determining that the base instruction has... Agent: Oracle International Corporation
20120089820 - Hybrid mechanism for more efficient emulation and method therefor: In a host system, a method for using instruction scheduling to efficiently emulate the operation of a target computing syste includes preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system. An instruction scheduling on the instruction sequence is performed,... Agent: International Business Machines Corporation
20120089821 - Debugging apparatus and method: A debugging apparatus and method are provided. The debugging apparatus may include a breakpoint setting unit configured to store a first instruction corresponding to a breakpoint in a table, stop a program currently being executed, and insert a breakpoint instruction including current location information of the first instruction into the... Agent:
20120089822 - Information processing device and emulation processing program and method: An emulation processing method causing a computer including a first and a second processor to execute emulation processing, the emulation processing method includes: calculate a next instruction address next to a received instruction address, and transmit, to the second processor, the calculated instruction address and instruction information read out on... Agent: Fujitsu Limited
20120089823 - Processing apparatus, compiling apparatus, and dynamic conditional branch processing method: A technology for reducing pipeline a control hazard is provided. A conditional branch is processed through a conditional branch prediction, and a predetermined conditional branch prediction, which is determined as incorrect, may be modified through a following test for the conditional branch prediction, thereby reducing the pipeline control hazard quickly... Agent: Samsung Electronics Co., Ltd.,
20120089824 - Processor and vector load instruction execution method: Provided is a processor including an instruction issue unit that issues a vector load instruction read from a main memory based on branch target prediction of a branch target in a branch instruction, a data acquisition unit that starts issue of a plurality of acquisition requests for acquiring a plurality... Agent:04/05/2012 > 9 patent applications in 7 patent subcategories.
20120084532 - Memory accelerator buffer replacement method and system: A microcontroller using an optimized buffer replacement strategy comprises a memory configured to store instructions, a processor configured to execute said program instructions, and a memory accelerator operatively coupled between the processor and the memory. The memory accelerator is configured to receive an information request and overwrite the buffer from... Agent: Nxp B.v.
20120084533 - Efficient parallel floating point exception handling in a processor: Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the... Agent:
20120084534 - System and method for fast branching using a programmable branch table: Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table... Agent: Juniper Networks, Inc.
20120084535 - Opcode space minimizing architecture utilizing instruction address to indicate upper address bits: Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have... Agent: International Business Machines Corporation
20120084536 - Primitives to enhance thread-level speculation: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write... Agent:
20120084538 - Methodology and framework for run-time coverage measurement of architectural events of a microprocessor: A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided.... Agent: Ibm Corporation
20120084537 - System and method for execution based filtering of instructions of a processor to manage dynamic code optimization: A filter executing on a processor monitors instructions executing on the processor to identify instructions that will benefit from performance tuning. Filtering instructions before analysis for performance tuning reduces overhead by identifying candidates for performance tuning with low cost monitoring before expending resources on analysis so that only instructions that... Agent: International Business Machines Corporation
20120084539 - Method and sytem for predicate-controlled multi-function instructions: Techniques are disclosed for executing conditional computer instructions in an efficient manner that reduces bubbles and idle states. In one embodiment, dual-function instruction execution is disclosed where the dual-function instruction has two possible functions (or operations), the choice of which is controlled by a predicate value with a true or... Agent:
20120084540 - Dynamically adjusting pipelined data paths for improved power management: A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to... Agent: International Business Machines CorporationPrevious industry: Electrical computers and digital processing systems: memory
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