|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) March listing by industry category 03/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 03/29/2012 > 25 patent applications in 17 patent subcategories.
20120079233 - Vector logical reduction operation implemented on a semiconductor chip: A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on... Agent:
20120079234 - Performing computations in a distributed infrastructure: The present invention extends to methods, systems, and computer program products for performing computations in a distributed infrastructure. Embodiments of the invention include a general purpose distributed computation infrastructure that can be used to perform efficient (in-memory), scalable, failure-resilient, atomic, flow-controlled, long-running state-less and state-full distributed computations. Guarantees provided by... Agent: Microsoft Corporation
20120079235 - Application scheduling in heterogeneous multiprocessor computing platforms: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor... Agent:
20120079236 - Scalable and programmable processor comprising multiple cooperating processor units: A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The... Agent:
20120079238 - Data processing device: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed... Agent: Renesas Electronics Corporation
20120079237 - Saving values corresponding to parameters passed between microcode callers and microcode subroutines from microcode alias locations to a destination storage location: An apparatus of one aspect includes a microcode storage, a microcode subroutine stored in the microcode storage, and a microcode caller of the microcode subroutine stored in the microcode storage. The microcode caller has a save microinstruction that indicates a destination storage location. The apparatus also includes microcode alias locations.... Agent:
20120079239 - Timing module: A timing module and a microcontroller. An independent processing unit, which is provided as a component of at least one closed-loop control circuit, is integrated in the timing module.... Agent:
20120079240 - Reduced-level shift overflow detection: A processor includes a shift overflow detector for rapidly detecting overflows that may result during execution of a shift instruction. Shift indication signals are generated in response to changes in logic state between adjacent pairs of bits of a received shift data word. A received shift amount is decoded to... Agent:
20120079241 - Instruction execution based on outstanding load operations: One embodiment of the present invention sets forth a technique for scheduling thread execution in a multi-threaded processing environment. A two-level scheduler maintains a small set of active threads called strands to hide function unit pipeline latency and local memory access latency. The strands are a sub-set of a larger... Agent:
20120079243 - Next-instruction-type-field: A graphics processing unit core 26 includes a plurality of processing pipelines 38, 40, 42, 44. A program instruction of a thread of program instructions being executed by a processing pipeline includes a next-instruction-type field 36 indicating an instruction type of a next program instruction following the current program instruction... Agent: Arm Limited
20120079242 - Processor power management based on class and content of instructions: A processor and method are disclosed. In one embodiment the processor includes a prefetch buffer that stores macro instructions. The processor also includes a clock circuit that can provide a clock signal for at least some of the functional units within the processor. The processor additionally includes macro instruction decode... Agent:
20120079246 - Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit... Agent:
20120079245 - Dynamic optimization for conditional commit: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit... Agent:
20120079244 - Method and apparatus for universal logical operations: An apparatus and method are described for performing arbitrary logical operations specified by a table. For example, one embodiment of a method for performing a logical operation on a computer processor comprises: reading data from each of two or more source operands; combining the data read from the source operands... Agent:
20120079247 - Dual register data path architecture: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that... Agent:
20120079248 - Aliased parameter passing between microcode callers and microcode subroutines: An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the... Agent:
20120079249 - Training decode unit for previously-detected instruction type: In an embodiment, a decode unit includes multiple decoders configured to decode different types of instructions. One or more of the decoders may be complex decoders, and the decode unit may disable the complex decoders if an instruction of the corresponding type is not being decoded. In an embodiment, the... Agent:
20120079250 - Functional unit capable of executing approximations of functions: A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit.... Agent:
20120079251 - Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions: A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.... Agent:
20120079253 - Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation: A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add... Agent:
20120079252 - Performing a multiply-multiply-accumulate instruction: In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding... Agent:
20120079254 - Debugging of a data processing apparatus: A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data... Agent: Arm Limited
20120079255 - Indirect branch prediction based on branch target buffer hysteresis: Methods and apparatus to perform efficient indirect branch prediction operations are described. In one embodiment, a branch target buffer (BTB) stored a target address and a bimodal hysteresis counter for an indirect branch that has been encountered by a front-end of the processor during a time period. An indirect branch... Agent:
20120079256 - Interrupt suppression: A processor receives interrupts of a same type from hardware. The processor determines a rate at which the interrupts are being received. The processor compares the rate at which the interrupts are being received to a threshold rate. In response to determining that the rate at which the interrupts are... Agent:
20120079257 - Methods and systems that defer exception handling: Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set.... Agent:03/22/2012 > 10 patent applications in 8 patent subcategories.
20120072699 - Logic cell array and bus system: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate... Agent:
20120072701 - Method macro expander: One embodiment of the present invention sets forth a [TODO once claims are reviewed]... Agent:
20120072700 - Multi-level register file supporting multiple threads: A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each... Agent: International Business Machines Corporation
20120072702 - Prefetcher with arbitrary downstream prefetch cancelation: A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation... Agent:
20120072703 - Split path multiply accumulate unit: In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the... Agent:
20120072704 - \"or\" bit matrix multiply vector instruction: A processor is operable to execute a bit matrix multiply instruction. In further examples, the processor is operable to perform a vector bit matrix multiply instruction, and is a part of a computerized system.... Agent: Cray Inc.
20120072706 - Microcode for transport triggered architecture central processing units: The different advantageous embodiments provide an apparatus comprising a central processing unit, a microcode store, and a number of functional units. The central processing unit utilizes transport triggered architecture and is configured to execute microcoded instructions that allow a single instruction to be executed as multiple instructions. The microcode store... Agent: The Boeing Company
20120072705 - Obtaining and releasing hardware threads without hypervisor involvement: A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to... Agent: International Business Machines Corporation
20120072707 - Scaleable status tracking of multiple assist hardware threads: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware... Agent: International Business Machines Corporation
20120072708 - History based pipelined branch prediction: Systems and methods for history based pipelined branch prediction. In one embodiment, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available... Agent:03/15/2012 > 9 patent applications in 8 patent subcategories.
20120066476 - Micro-operation processing system and data writing method thereof: A data writing method and a micro-operation processing system are provided. The micro-operation processing system is adapted to access a plurality of registers and each of the registers defines at least one logic storing area. The data writing method comprises the following steps: executing a first micro-operation; selecting a target... Agent: Rdc Semiconductor Co., Ltd.
20120066477 - Advanced processor with mechanism for packet distribution at high line rate: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores... Agent: Netlogic Microsystems, Inc.
20120066478 - Method for fast parallel instruction length determination: The present invention provides a method and apparatus that may be used for parallel instruction length decoding. One embodiment of the method includes concurrently determining a plurality of masks identifying bytes in a plurality of candidate instructions. Each mask uses a different byte in a first fetch window as a... Agent:
20120066479 - Methods and apparatus for handling switching among threads within a multithread processor: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution... Agent:
20120066480 - Processor: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment... Agent: Sony Corporation
20120066481 - Dynamic instruction splitting: A data processing apparatus and method are provided. The data processing apparatus is configured to perform data processing operations in response to data processing instructions including a multiple operation instruction, in response to which multiple data processing operations are performed. The data processing apparatus comprises two or more data processing... Agent: Arm Limited
20120066482 - Macroscalar processor architecture: A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an... Agent:
20120066483 - Computing device with asynchronous auxiliary execution unit: A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the... Agent: International Business Machines Corporation
20120066484 - Patching method and patching device in multi-core environment: A patching mechanism in a multi-core environment that includes sending an inter-core non-maskable interrupt to each target Virtual Central Processing Unit (CPU) (VCPU) in a target VCPU group, which share a code segment, so that said each target VCPU enters a patch synchronization state in response to the inter-core non-maskable... Agent: Huawei Technologies Co., Ltd.03/08/2012 > 6 patent applications in 5 patent subcategories.
20120060016 - Vector loads from scattered memory locations: Mechanisms for performing a scattered load operation are provided. With these mechanisms, a gather instruction is receive in a logic unit of a processor, the gather instruction specifying a plurality of addresses in a memory from which data is to be loaded into a target vector register of the processor.... Agent: International Business Machines Corporation
20120060015 - Vector loads with multiple vector elements from a same cache line in a scattered load operation: Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of data element address portions that specify a plurality of data elements to be accessed using the single extended address.... Agent: International Business Machines Corporation
20120060017 - Processor: A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including... Agent:
20120060018 - Collective operations in a file system based execution model: A mechanism is provided for group communications using a MULTI-PIPE synthetic file system. A master application creates a multi-pipe synthetic file in the MULTI-PIPE synthetic file system, the master application indicating a multi-pipe operation to be performed. The master application then writes a header-control block of the multi-pipe synthetic file... Agent: International Business Machines Corporation
20120060019 - Reduction operation device, a processor, and a computer system: A reduction operation device detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation of a parallel processing. The reduction operation device is inputted a plurality of the synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and... Agent: Fujitsu Limited
20120060020 - Vector index instruction for processing vectors: The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a start value and an increment value, and optionally receiving a predicate vector with N elements as inputs. The processor then executes the vector instruction. Executing the vector instruction causes the processor to generate... Agent: Apple Inc.03/01/2012 > 6 patent applications in 6 patent subcategories.
20120054468 - Processor, apparatus, and method for memory management: An apparatus and method that includes a single memory as a VLIW instruction cache and CGA configuration memory is provided. Data is provided from a storage unit to a processing core that is capable of processing data in a first mode and a second mode. If the processing core is... Agent:
20120054469 - Blade server apparatus: A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and... Agent: Hitachi, Ltd.
20120054470 - Optimization system, optimization method, and compiler program: A system, method and article of manufacture of increasing access speed of frequently accessed variables (symbols) in a dynamic language program. The system includes a range identifying unit to identify a range for communizing symbol accesses in the program; an instruction generating unit to generate instructions to access a symbol... Agent: International Business Machines Corporation
20120054471 - Method and system for using external storage to amortize cpu cycle utilization: A method and system for using external storage to amortize CPU cycle utilization, wherein translated instructions are stored in a storage medium and subsequently accessed on a subsequent execution of a non-native application in order to amortize CPU cycles used in generating the translated instructions.... Agent:
20120054472 - Automatic identification of bottlenecks using rule-based expert knowledge: Execution states of tasks are inferred from collection of information associated with runtime execution of a computer system. Collection of information may include infrequent samples of executing tasks, the samples which may provide inaccurate executing states. One or more tasks may be aggregated by one or more execution states for... Agent: International Business Machines Corporation
20120054473 - Processor: There is provided a processor comprising a plurality of registers, an acquisition unit, a calculation unit, a pipeline register, and a storage unit, wherein in a case in which a register indicated by source register information included in a second instruction and a register indicated by destination register information included... Agent: Canon Kabushiki KaishaPrevious industry: Electrical computers and digital processing systems: memory
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