|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) February patent applications/inventions, industry category 02/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/23/2012 > 7 patent applications in 7 patent subcategories. patent applications/inventions, industry category
20120047349 - Data transfer system: A data transfer system includes: a plurality of processors; and a plurality of data transfer units that executes a data transfer from one processor to other processor via a plurality of input ports and a plurality of output ports. The data transfer unit includes: an arbitration unit that executes arbitration... Agent: Nec Corporation
20120047350 - Controlling simd parallel processors: ii) a compiler for verifying and converting the plurality of the single line instructions into an executable set of commands for the parallel processor, wherein the processing apparatus is arranged to process each single line instruction which specifies an operation and an active group of selected data processing elements for... Agent:
20120047351 - Data processing system having selective redundancy and method therefor: A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the... Agent:
20120047352 - Processor: A processor includes: an instruction buffer which stores the instructions to be dispatched to the arithmetic units; a dependency detecting unit which (i) detects a first dependency and a second dependency and (ii) determines an instruction group including the instructions to be dispatched to the corresponding arithmetic units, the first... Agent: Panasonic Corporation
20120047353 - System and method providing run-time parallelization of computer software accommodating data dependencies: A system and method of parallelizing programs employs runtime instructions to identify data accessed by program portions and to assign those program portions to particular processors based on potential overlap between the access data. Data dependence between different program portions may be identified and used to look for pending “predicate”... Agent:
20120047354 - Information processing apparatus and information processing method: According to one embodiment, an information processing apparatus includes: a first verification section configured to perform true-false determination for a predetermined verification target using a verification item obtained by combining specified one of plural verification libraries respectively defining plural verification matters and an affirmative operator or a negative operator; a... Agent: Toshiba Tec Kabushiki Kaisha
20120047355 - Information processing apparatus performing various bit operation and information processing method thereof: An information processing apparatus operates data stored in an input register for each bit and stores a result thereof in an output register. A selector circuit selects output data of a bit from input data of 128 bits in the input register. An AND circuit outputs, only when data from... Agent: Sony Corporation02/16/2012 > 6 patent applications in 6 patent subcategories. patent applications/inventions, industry category
20120042150 - Multiprocessor system-on-a-chip for machine vision algorithms: A multiprocessor system includes a main memory and multiple processing cores that are configured to execute software that uses data stored in the main memory. In some embodiments, the multiprocessor system includes a data streaming unit, which is connected between the processing cores and the main memory and is configured... Agent: Primesense Ltd.
20120042151 - Processor having execution core sections operating at different clock rates: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and... Agent:
20120042152 - Elimination of read-after-write resource conflicts in a pipeline of a processor: An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict... Agent:
20120042153 - Data processing system having temporal redundancy and method therefor: In a data processing system having execution circuitry, a method includes providing a reference instruction to the execution circuitry, the reference instruction having an operand; providing a cross-check instruction to the execution circuitry; executing the reference instruction to obtain a first result, wherein, during the step of executing the reference... Agent:
20120042154 - Illegal mode change handling: A data processing system 2 supporting multiple modes of operation is provided with illegal change detecting circuitry 22 which detects attempts by program instructions to perform an illegal change of mode, e.g. such as a change to a higher level of privilege in response to execution of a mode changing... Agent: Arm Limited
20120042155 - Methods and apparatus for proactive branch target address cache management: A multiple stage branch prediction system includes a branch target address cache (BTAC) and a branch predictor circuit. The BTAC is configured to store a BTAC entry. The branch predictor circuit is configured to store state information. The branch predictor circuit utilizes the state information to predict the direction of... Agent: Qualcomm Incorporated02/09/2012 > 8 patent applications in 8 patent subcategories. patent applications/inventions, industry category
20120036336 - Information processor: The present invention provides an information processing apparatus and an integrated circuit which realize parallel execution of different processing systems, and which do not require the provision of a dedicated memory storing instructions for common processing The information processing apparatus comprises: a plurality of processor elements; an instruction memory storing... Agent:
20120036337 - Processor on an electronic microchip comprising a hardware real-time monitor: A processor on an electronic microchip is capable of executing mathematical processes, each of said processes being associated with a priority, and includes means for the management of the processes, the means for the management of the processes taking the form of hardware, the management of the processes comprising the... Agent: Thales
20120036338 - Facilitating processing in a computing environment using an extended drain instruction: An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.... Agent: International Business Machines Corporation
20120036339 - Asynchronous assist thread initiation: A method of data processing includes a processor of a data processing system executing a controlling thread of a program and detecting occurrence of a particular asynchronous event during execution of the controlling thread of the program. In response to occurrence of the particular asynchronous event during execution of the... Agent: International Business Machines Corporation
20120036340 - Data processing apparatus and method using checkpointing: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint... Agent: Arm Limited
20120036341 - Data processing apparatus, for example using modes: Embodiments of the invention relate to a data processing apparatus including a processor adapted to operate under control of an executable comprising instructions, and in any of a plurality of operating modes including a non-privileged mode and a privileged mode, the apparatus comprising: means for storing a plurality of stacks;... Agent: Cambridge Consultants Ltd.
20120036342 - Method and apparatus for handling lane crossing instructions in an execution pipeline: The present invention provides a method and apparatus for handling lane-crossing instructions in an execution pipeline. One embodiment of the method includes conveying bits of an instruction from a register to an execution stage in a pipeline along a first data path that includes a lane crossing stage configured to... Agent:
20120036343 - Electronic apparatus and meter operable during program updating: There are provided an electronic apparatus and a meter which are operable during the updating of an operating program and firmware. The electronic apparatus operable during program updating includes an operation unit performing a preset operation, a micro controller controlling an operation result of the operation unit to be stored... Agent: Samsung Electro-mechanics Co., Ltd.02/02/2012 > 6 patent applications in 6 patent subcategories. patent applications/inventions, industry category
20120030448 - Single instruction multiple date (simd) processor having a plurality of processing elements interconnected by a ring bus: A single instruction multiple data (SIMD) processor having a plurality of processing elements and including: a splitting unit for splitting an address of the read-only parameter data in the data memory into a first part and a second part at a bit position corresponding to the number of the processor... Agent: Nec Corporation
20120030449 - Data tag control for quantum-dot cellular automata: The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data... Agent:
20120030450 - Method and system for parallel computation of linear sequential circuits: A method and system for parallel computation of a linear sequential circuit (LSC) based on a state transition matrix is disclosed herein. A multistep state transition matrix and a multistep output generation matrix can be pre-computed and stored in association with the linear sequential circuit. The multiple state transitions and... Agent: Lsi Corporation
20120030451 - Parallel and long adaptive instruction set architecture: An Parallel and Long Adaptive Instruction Set Architecture (PALADIN) is provided to optimize packet processing. The Instruction Set Architecture (ISA) includes instructions such as aggregate comparison, comparison OR, comparison AND and bitwise instructions. The ISA also includes dedicated packet processing instructions such as hash, predicate, select, checksum and time to... Agent: Broadcom Corporation
20120030452 - Modifying commands: The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the... Agent: Micron Technology, Inc.
20120030453 - Information processing apparatus, cache apparatus, and data processing method: A more efficient technique is provided in an information processing apparatus which executes processing using pipelines. An information processing apparatus according to this invention includes a first pipeline, second pipeline, processing unit, and reorder unit. The first pipeline has a plurality of first nodes, and shifts first data held in... Agent: Canon Kabushiki KaishaPrevious industry: Electrical computers and digital processing systems: memory
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