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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) December patent applications/inventions, industry category 12/11

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
12/29/2011 > 29 patent applications in 17 patent subcategories.

20110320765 - Variable width vector instruction processor: A computer processor, method, and computer program product for executing vector processing instructions on a variable width vector register file. An example embodiment is a computer processor that includes an instruction execution unit coupled to a variable width vector register file which contains a number of vector registers, the width... Agent: International Business Machines Corporation

20110320766 - Apparatus, method, and system for improving power, performance efficiency by coupling a first core type with a second core type: An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution... Agent:

20110320768 - Method of, and apparatus for, mitigating memory bandwidth limitations when performing numerical calculations: There is provided a method of, and apparatus for, processing a computation on a computing device comprising at least one processor and a memory, the method comprising: storing, in said memory, plural copies of a set of data, each copy of said set of data having a different compression ratio... Agent: Maxeler Technologies, Ltd.

20110320769 - Parallel computing device, information processing system, parallel computing method, and information processing device: A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical... Agent:

20110320767 - Parallelization of online learning algorithms: Methods, systems, and media are provided for a dynamic batch strategy utilized in parallelization of online learning algorithms. The dynamic batch strategy provides a merge function on the basis of a threshold level difference between the original model state and an updated model state, rather than according to a constant... Agent: Microsoft Corporation

20110320770 - Data processing device: An internal buffer is provided for a DRP core. A selector SEL switches input/output destination of the DRP core between external memory and an internal buffer. Control software executed by a CPU core receives information a pipeline of configurations for a sequence of target processing and generates combinations as to... Agent: Fuji Xerox Co., Ltd.

20110320771 - Instruction unit with instruction buffer pipeline bypass: A circuit arrangement and method selectively bypass an instruction buffer for selected instructions so that bypassed instructions can be dispatched without having to first pass through the instruction buffer. Thus, for example, in the case that an instruction buffer is partially or completely flushed as a result of an instruction... Agent: International Business Machines Corporation

20110320775 - Accelerating execution of compressed code: Methods and apparatus relating to accelerating execution of compressed code are described. In one embodiment, a two-level embedded code decompression scheme is utilized which eliminates bubbles, which may increase speed and/or reduce power consumption. Other embodiments are also described and claimed.... Agent:

20110320772 - Controlling the selectively setting of operational parameters for an adapter: An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device... Agent: International Business Machines Corporation

20110320773 - Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will... Agent: International Business Machines Corporation

20110320774 - Operand fetching control as a function of branch confidence: A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as... Agent: International Business Machines Corporation

20110320776 - Mechanism for irrevocable transactions: A method and apparatus for designating and handling irrevocable transactions is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner... Agent:

20110320777 - Direct memory access engine physical memory descriptors for multi-media demultiplexing operations: The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from... Agent:

20110320778 - Centralized serialization of requests in a multiprocessor system: Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch... Agent: International Business Machines Corporation

20110320780 - Hybrid compare and swap/perform locked operation queue algorithm: Systems, methods, and computer program products are disclosed for intermixing different types of machine instructions. One embodiment of the invention provides a protocol for intermixing the different types of machine instructions. By adhering to the protocol, different types of machine instructions may be intermixed to concurrently update data structures without... Agent: International Business Machines Corporation

20110320779 - Performance monitoring in a shared pipeline: A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at... Agent: International Business Machines Corporation

20110320781 - Dynamic data synchronization in thread-level speculation: In one embodiment, the present invention introduces a speculation engine to parallelize serial instructions by creating separate threads from the serial instructions and inserting processor instructions to set a synchronization bit before a dependence source and to clear the synchronization bit after a dependence source, where the synchronization bit is... Agent:

20110320782 - Program status word dependency handling in an out of order microprocessor design: A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with... Agent: International Business Machines Corporation

20110320784 - Verification of processor architectures allowing for self modifying code: A verification operation including generating a predefined instruction, initializing a relevant self modifying code (SMC) target memory location to form an SMC trap, binding the SMC trap to the predefined instruction to form an SMC trap source and propagating initialization of instruction code into the SMC trap source.... Agent: International Business Machines Corporation

20110320783 - Verification using opcode compare: A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate... Agent: International Business Machines Corporation

20110320785 - Binary rewriting in software instruction cache: Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the... Agent: International Business Machines Corporation

20110320786 - Dynamically rewriting branch instructions in response to cache line eviction: Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A... Agent: International Business Machines Corporation

20110320787 - Indirect branch hint: A processor implements an apparatus and a method for predicting an indirect branch address. A target address generated by an instruction is automatically identified. A predicted next program address is prepared based on the target address before an indirect branch instruction utilizing the target address is speculatively executed. The apparatus... Agent: Qualcomm Incorporated

20110320788 - Method and apparatus for branch reduction in a multithreaded packet processor: A method and apparatus for branch reduction in a multithreaded packet processor is presented. An instruction is executed which includes testing of a branch flag. The branch flag references a configuration bit vector wherein each bit in the configuration bit vector corresponds to a respective feature. When said branch flag... Agent: Avaya Inc.

20110320789 - Method and apparatus for high performance cache translation look-aside buffer tlb lookups using multiple page size prediction: A computer processing system method and apparatus having a processor employing an operating system (O/S) multi-task control between multiple user programs and which ensures that the programs do not interfere with each other, said computing processing system having a branch multiple page size prediction mechanism which predicts a page size... Agent: International Business Machines Corporation

20110320790 - Link stack repair of erroneous speculative update: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register... Agent: Qualcomm Incorporated

20110320791 - Method and apparatus to limit millicode routine end branch prediction: A computing system method, program and hardware for correlation of millicode predictions with specific millicode routines receives architected millicode and stores the millicode in internal memory. The computer systems processors' pipeline is employed to predict and select a branch target buffer's (BTB) target address. A computer millicode control enabling an... Agent: International Business Machines Corporation

20110320793 - Operating system aware branch predictor using a dynamically reconfigurable branch history table: A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The... Agent: International Business Machines Corporation

20110320792 - State machine-based filtering of pattern history tables based on distinguishable pattern detection: Machine-based filtering of a pattern history table includes identifying a matching previous occurrence of a current branch instruction in an address history vector (AHV), the AHV storing addresses, or partial addresses, of most recently occurring branch instructions. In response to determining a direction history of the previous occurrence matches a... Agent: International Business Machines Corporation

12/22/2011 > 12 patent applications in 11 patent subcategories.

20110314254 - Method for vector processing: The present application relates to a method for processing data in a vector processor. The present application relates also to a vector processor for performing said method and a cellular communication device comprising said vector processor. The method for processing data in a vector processor comprises executing segmented operations on... Agent: Nxp B.v.

20110314255 - Message broadcast with router bypassing: A processor and method for broadcasting data among a plurality of processing cores is disclosed. The processor includes a plurality of processing cores connected by point-to-point connections. A first of the processing cores includes a router that includes at least an allocation unit and an output port. The allocation unit... Agent:

20110314256 - Data parallel programming model: Described herein are techniques for enabling a programmer to express a call for a data parallel call-site function in a way that is accessible and usable to the typical programmer. With some of the described techniques, an executable program is generated based upon expressions of those data parallel tasks. During... Agent: Microsoft Corporation

20110314257 - Distributed micro instructions set processor architecture for high-efficiency signal processing: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used... Agent:

20110314258 - Method and apparatus for operating a programmable logic controller (plc) with decentralized, autonomous sequence control: A method for operating a programmable logic controller (PLC), and a programmable logic controller (PLC) for a processing plant with a central data processing unit and a sequence control that reads in, processes input data from inputs, and outputs the processed output data to outputs. The data processing unit performs... Agent: Bachmann Gmbh

20110314259 - Operating a stack of information in an information handling system: A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to... Agent: International Business Machines Corporation

20110314260 - High-word facility for extending the number of general purpose registers available to instructions: A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a... Agent: International Business Machines Corporation

20110314261 - Prefetch of attributes in evaluating access control requests: In an embodiment, a method is provided for prefetching attributes used in access control evaluation. In this method, an access control policy that comprises rules is retrieved. These rules further comprise parameters. At least one of the rules is categorized into a class from multiple classes based on at least... Agent: Sap Ag

20110314262 - Prefetch request circuit: A prefetch request circuit is provided in a processor device. The processor device has hierarchized storage areas and can prefetch data of address to be used between appropriate storage areas among the storage areas, when executing respective instruction flows obtained by multi-flow expansion for one instruction at a time of... Agent: Fujitsu Limited

20110314263 - Instructions for performing an operation on two operands and subsequently storing an original value of operand: An arithmetic/logical instruction is executed having interlocked memory operands. when executed obtains a second operand from a location in memory, and saves a temporary copy of the second operand, the execution performs an arithmetic or logical operation based on the second operand and a third operand and stores the result... Agent: International Business Machines Corporation

20110314264 - Key allocation when tracing data processing systems: A trace unit is provided which is configured to generate items of trace data indicative of processing activities, of a data processing unit. The trace unit comprises a trace indexing unit configured to associate an index value with at least a subset of the items of trace data generated by... Agent: Arm Limited

20110314265 - Processors operable to allow flexible instruction alignment: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported... Agent: Altera Corporation

12/15/2011 > 6 patent applications in 6 patent subcategories.

20110307684 - Image processing address generator: An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor includes an address generator operatively attached to the memory to access the memory. The address generator is adapted for calculating... Agent:

20110307685 - Processor for large graph algorithm computations and matrix operations: A multiprocessor system and method for performing matrix operations includes multiple processors cooperatively performing a sparse matrix operation. Distributed among the processors are non-zero matrix elements of first and second sparse matrices. Mapped across the processors are the matrix elements of a results matrix. Each processor receives, from the other... Agent:

20110307686 - Method for instructing a data processor to process data: A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format.... Agent: Panasonic Corporation

20110307687 - In-lane vector shuffle instructions: In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions... Agent:

20110307688 - Synthesis system for pipelined digital circuits: Computer-implemented methods and systems for synthesizing a hardware description for a pipelined datapath for a digital circuit. A transactional datapath specification framework and a transactional design automation system automatically synthesize pipeline implementations. The transactional datapath specification framework captures an abstract datapath, whose execution semantics is interpreted as a sequence of... Agent: Carnegie Mellon University

20110307689 - Processor support for hardware transactional memory: A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality... Agent:

12/08/2011 > 8 patent applications in 7 patent subcategories.

20110302390 - Systems and methods for processing communications signals fusing parallel processing: Systems and methods for performing processing of communications signals on multi-processor architectures. The system consists of a digital interface that translate numbers that represent a waveform in some format to analog signals for use in transmission and translating analog signals to numbers representing those waveforms in some format that can... Agent:

20110302391 - Digital signal processor: A digital signal processor comprises an instruction analysis unit, a digital signal processor (DSP) core and a memory unit. The instruction analysis unit receives an instruction and determines the required bit width M for the data process corresponding to the instruction. The DSP core performs the M-bit data process based... Agent: Sentetic Corporation

20110302392 - Instruction tracking system for processors: A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains... Agent: International Business Machines Corporation

20110302393 - Control systems and data processing method: When executing sequential processing such as a ladder logic, converting a program formed of an instruction set of another processor to a program executable by an own processor in software and then conducting processing lowers the real time property. In a control system, a storage unit stores a program for... Agent:

20110302394 - System and method for processing regular expressions using simd and parallel streams: A system and method for performing regular expression computations includes loading a plurality of input values corresponding to one or more input streams as elements of a vector register implemented on programmable storage media. New state indexes are computed using the input values, and current state values corresponding to different... Agent: International Business Machines Corporation

20110302395 - Hardware assist thread for dynamic performance profiling: A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an... Agent: International Business Machines Corporation

20110302396 - Image processing apparatus that performs processing according to instruction defining the processing, control method for the apparatus, and storage medium: An image processing apparatus which makes it possible to select a plurality of instructions at a time, and connect a plurality of documents together so that they can be processed as one document. The image processing apparatus has a reading unit, which reads an image on an original to generate... Agent: Canon Kabushiki Kaisha

20110302397 - Method and apparatus for improved secure computing and communications: A computing and communications system and method may comprise a primitive recursive function computing engine including an instruction set architecture prohibiting loop operations that continue for an indefinite time. The system and method may further comprise the instruction set architecture comprising system identifiers selected from a group comprising things, places,... Agent:

12/01/2011 > 13 patent applications in 11 patent subcategories.

20110296137 - Performing a deterministic reduction operation in a parallel computer: A parallel computer that includes compute nodes having computer processors and a CAU (Collectives Acceleration Unit) that couples processors to one another for data communications. In embodiments of the present invention, deterministic reduction operation include: organizing processors of the parallel computer and a CAU into a branched tree topology, where... Agent: International Business Machines Corporation

20110296138 - Fast remote communication and computation between processors: A method, system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the... Agent: International Business Machines Corporation

20110296139 - Performing a deterministic reduction operation in a parallel computer: Performing a deterministic reduction operation in a parallel computer that includes compute nodes, each of which includes computer processors and a CAU (Collectives Acceleration Unit) that couples computer processors to one another for data communications, including organizing processors and a CAU into a branched tree topology in which the CAU... Agent: International Business Machines Corporation

20110296141 - Persistent finite state machines from pre-compiled machine code instruction sequences: A processor, integrated with re-configurable logic and memory elements, is disclosed which is to be used as part of a shared memory, multiprocessor computer system. The invention utilizes the re-configurable elements to construct persistent finite state machines based on information decoded by the invention from sequences of CISC or RISC... Agent:

20110296140 - Risc processor register expansion method: A RISC processor register expansion method is disclosed to include the steps of: a) designing an instruction format having multiple register fields to have the total bits consumed by the register fields to be designed into two bits combinations respectively corresponding to two register banks, wherein the first bits combination... Agent: National Chung Cheng University

20110296142 - Processor and method providing instruction support for instructions that utilize multiple register windows: A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction execution unit that, during operation, receives instructions for execution from the instruction fetch unit and executes a... Agent:

20110296143 - Pipeline processor and an equal model conservation method: A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions... Agent:

20110296144 - Reducing data hazards in pipelined processors to provide high processor utilization: A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions... Agent: Micron Technology, Inc.

20110296145 - Pipelined digital signal processor: Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed... Agent:

20110296146 - Hardware instructions to accelerate table-driven mathematical function evaluation: A set of instructions for implementation in a floating-point unit or other computer processor hardware is disclosed herein. In one embodiment, an extended-range fused multiply-add operation, a first look-up operation, and a second look-up operation are each embodied in hardware instructions configured to be operably executed in a processor. These... Agent: International Business Machines Corporation

20110296147 - Method of testing computer, computer test apparatus and non-transitory computer-readable medium: A method of testing a computer, the method has designating a register as an input-only register having a setting of a value which does not cause an exception interruption with an execution of a specific type of instruction, generating a test instruction array having a plurality of instructions for a... Agent: Fujitsu Limited

20110296148 - Transactional memory system supporting unbroken suspended execution: Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response... Agent: International Business Machines Corporation

20110296149 - Instruction set architecture extensions for performing power versus performance tradeoffs: Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or... Agent: International Business Machines Corporation

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