|Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents - Monitor Patents|
USPTO Class 712 | Browse by Industry: Previous - Next | All
11/2011 | Recent | 14: Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) November recently filed with US Patent Office 11/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/24/2011 > 7 patent applications in 5 patent subcategories. recently filed with US Patent Office
20110289297 - Instruction scheduling approach to improve processor performance: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at... Agent: International Business Machines Corporation
20110289298 - Semiconductor circuit and designing apparatus: A semiconductor circuit includes a memory which stores data; a processing device which executes a program, writes argument data of a function of the program into the memory referring to an address stored in a stack pointer, when a value of a program counter, which indicates an address of the... Agent: Fujitsu Semiconductor Limited
20110289300 - Indirect branch target predictor that prevents speculation if mispredict is expected: In one embodiment, a processor implements an indirect branch target predictor to predict target addresses of indirect branch instructions. The indirect branch target predictor may store target addresses generated during previous executions of indirect branches, and may use the stored target addresses as predictions for current indirect branches. The indirect... Agent:
20110289299 - System and method to evaluate a data value as an instruction: A system and method to evaluate a data value as an instruction is disclosed. For example, an apparatus configured to execute program code includes an execute unit configured to execute a first instruction associated with a location of a second instruction. The first instruction is identified by a program counter.... Agent: Qualcomm Incorporated
20110289302 - Data processing device and method: Overhead is significant when a timestamp according to a reference time is inserted. In view of this, there is provided an LSI which includes: a first time information conversion unit which converts, into time information of a reference time, time information from a first trace data source; a second time... Agent: Panasonic Corporation
20110289301 - Tracing flow of data in a distributed computing application: A method is provided for tracing dataflow in a distributed computing application. For example, the method includes incrementally advancing a dataflow in a dataflow path of one or more dataflow paths according to two or more directives encoded in two or more data messages. The method further includes performing the... Agent: International Business Machines Corporation
20110289303 - Setjmp/longjmp for speculative execution frameworks: A process for check pointing in speculative execution frameworks, identifies calls to a set of setjmp/longjmp instructions to form identified calls to setjmp/longjmp, determines a control flow path between a call to a setjmp and a longjmp pair of instructions in the identified calls to setjmp/longjmp and replaces calls to... Agent: International Business Machines Corporation11/17/2011 > 11 patent applications in 8 patent subcategories. recently filed with US Patent Office
20110283089 - modularized micro processor design: A method and system of modularized design for a microprocessor are disclosed. Embodiments disclose modularization techniques, whereby the overall design of the execution unit of the processor is split into different functional modules. The modules are configured to function independent of each other. The microprocessor comprises different components such as... Agent:
20110283088 - Data processing apparatus and data processing method: A data processing apparatus includes a connecting unit that distributes the plurality of processing modules over the stages, and connects the plurality of processing modules such that a plurality of partial data are processed in parallel. The data processing apparatus detects, with respect to at least a part of the... Agent: Canon Kabushiki Kaisha
20110283087 - Image forming apparatus, image forming method, and computer readable medium storing control program therefor: A first processing unit is implemented by executing a first application program by using an internal computer in an environment where a first operating system is operating. The first processing unit performs a first process or an external service call in accordance with instruction information describing a process to be... Agent: Fuji Xerox Co., Ltd.
20110283086 - Streaming physics collision detection in multithreaded rendering software pipeline: A circuit arrangement, program product and method stream level of detail components between hardware threads in a multithreaded circuit arrangement to perform physics collision detection. Typically, a master hardware thread, e.g., a component loader hardware thread, is used to retrieve level of detail data for an object from a memory... Agent: International Business Machines Corporation
20110283090 - Instruction addressing using register address sequence detection: A circuit arrangement and method support efficient indexing into large register files by utilizing register address sequence detection, wherein register addresses to be used by an instruction are produced by concatenating a portion of the address that is contained in the instruction with another portion that is speculatively produced by... Agent: International Business Machines Corporation
20110283091 - Parallelizing sequential frameworks using transactions: Various technologies and techniques are disclosed for transforming a sequential loop into a parallel loop for use with a transactional memory system. Open ended and/or closed ended sequential loops can be transformed to parallel loops. For example, a section of code containing an original sequential loop is analyzed to determine... Agent: Microsoft Corporation
20110283092 - Getfirst and assignlast instructions for processing vectors: The described embodiments comprise a processor that executes vector instructions. In the described embodiments, while executing program code, the processor receives a vector instruction that indicates an input vector that includes N elements, wherein receiving the vector instruction comprises optionally receiving a predicate vector that includes N elements. The processor... Agent: Apple Inc.
20110283093 - Minimizing program execution time for parallel processing: According to one embodiment, an information processing apparatus comprises a storage storing program modules and parallel execution control description describing relationships of the program modules, a conversion module extracting a part relating to the program module from the parallel execution control description, and creating graph data structure creation information including... Agent: Kabushiki Kaisha Toshiba
20110283094 - Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit: A semiconductor device is capable of being coupled to a first debugger and a second debugger, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupled to the first chip. The... Agent: Renesas Electronics Corporation
20110283095 - Hardware assist thread for increasing code parallelism: Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already... Agent: International Business Machines Corporation
20110283096 - Register file supporting transactional processing: A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency. Responsive to the processor processing a second instruction in a transactional code section to obtain... Agent: International Business Machines Corporation11/10/2011 > 11 patent applications in 10 patent subcategories. recently filed with US Patent Office
20110276782 - Running subtract and running divide instructions for processing vectors: The described embodiments provide a processor for generating a result vector with subtracted or mathematically divided values from a first input vector. During operation, the processor receives the first input vector, a second input vector, and a control vector, and optionally receives a predicate vector. The processor then records a... Agent: Apple Inc.
20110276783 - Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations: Systems and methods for efficient execution of operations in a multi-threaded processor. Each thread may include a blocking instruction. A blocking instruction blocks other threads from utilizing hardware resources for an appreciable amount of time. One example of a blocking type instruction is a Montgomery multiplication cryptographic instruction. Each thread... Agent:
20110276785 - Byte code conversion acceleration device and a method for the same: Provided is a bytecode conversion acceleration device and a method for the same: allowing a reduction in the size of a storage unit for a look-up table including a decoding table, a link table and a native code table; increasing the number of bytecodes that can be processed by hardware... Agent:
20110276784 - Hierarchical multithreaded processing: In one embodiment, a current candidate thread is selected from each of multiple first groups of threads using a low granularity selection scheme, where each of the first groups includes multiple threads and first groups are mutually exclusive. A second group of threads is formed comprising the current candidate thread... Agent: Telefonaktiebolaget L M Ericsson (publ)
20110276786 - Shared prefetching to reduce execution skew in multi-threaded systems: Mechanisms are provided for optimizing code to perform prefetching of data into a shared memory of a computing device that is shared by a plurality of threads that execute on the computing device. A memory stream of a portion of code that is shared by the plurality of threads is... Agent: International Business Machines Corporation
20110276787 - Multithread processor, compiler apparatus, and operating system apparatus: A multithread processor for executing, in parallel, instructions included in a plurality of threads includes: a calculating group including a plurality of calculators each of which is for executing an instruction; instruction grouping units which classify, for each thread, the instructions included in the thread into groups each of which... Agent: Panasonic Corporation
20110276788 - Pipeline processor: A bypass circuit is provided in a pipeline processor. A pipeline register is provided between an instruction execution stage and a write-back stage. The pipeline register stores a data validity flag and a WRITE control flag to control writing data into a general purpose register unit. The data retained in... Agent: Kabushiki Kaisha Toshiba
20110276789 - Parallel processing of data: A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may... Agent: Google Inc.
20110276790 - Instruction support for performing montgomery multiplication: Techniques are disclosed relating to a processor including instruction support for performing a Montgomery multiplication. The processor may issue, for execution, programmer-selectable instruction from a defined instruction set architecture (ISA). The processor may include an instruction execution unit configured to receive instructions including a first instance of a Montgomery-multiply instruction... Agent:
20110276791 - Handling a store instruction with an unknown destination address during speculative execution: The described embodiments provide a system for executing instructions in a processor. While executing instructions in an execute-ahead mode, the processor encounters a store instruction for which a destination address is unknown. The processor then defers the store instruction. Upon encountering a load instruction while the store instruction with the... Agent: Oracle International Corporation
20110276792 - Resource flow computer: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are... Agent: Board Of Governors For Higher Education, State Of Rhode Island An Providence Plantations11/03/2011 > 10 patent applications in 8 patent subcategories. recently filed with US Patent Office
20110271076 - Optimizing task management: An electronic device includes a processing component and a task manager. The processing component is configurable for one of a single-core processing mode and a multi-core processing mode. The task manager determines a number of tasks running on the electronic device. The processor is configured to one of the single-core... Agent:
20110271077 - Processor and data collection method: A processor has a plurality of PEs (processing elements) that operate in parallel based on operation commands and an information collection unit that collects the data of the plurality of PEs, wherein each of the plurality of PEs holds data and a condition flag, supplies the data and the condition... Agent:
20110271078 - Processor structure of integrated circuit: A processor structure of integrated circuit is provided. The processor structure comprises at least one processor capable of configuring an operation component and at least one processor capable of configuring a storage component. The processor capable of configuring an operation component or the processor capable of configuring a storage component... Agent: Peking University Shenzhen Graduate School
20110271079 - Multiple-core processor supporting multiple instruction set architectures: A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when... Agent: International Business Machines Corporation
20110271080 - Computer system and method of adapting a computer system to support a register window architecture: A target computing system 10 is adapted to support a register window architecture, particularly for use when converting non-native subject code 17 instead into target code 21 executed by a target processor 13. A subject register stack data structure (an “SR stack”) 400 in memory has a plurality of frames... Agent: International Business Machines Corporation
20110271081 - Multimedia platform: A multimedia platform is discussed, which includes a first stacking unit including a first substrate and a multimedia processor, wherein the first substrate and the multimedia processor are stacked on the first stacking unit, a pattern and a via hole are formed on the first substrate, and the multimedia processor... Agent:
20110271083 - Microprocessor architecture and method of instruction decoding: A microprocessor architecture comprises an instruction decoding network for decoding in a first mode partially suppressed opcodes of a sequence of instructions, the opcodes comprising a first part containing parameters being invariant for each opcode of the sequence and a second part comprising a flag indicating an end of the... Agent: Freescale Semiconductor, Inc.
20110271082 - Performing actions on frame entries in response to receiving bulk instruction: Various example embodiments are disclosed. According to an example embodiment, a switch may comprise an instruction decode stage and a lookup stage. The instruction decode stage may be configured to receive a bulk instruction identifying an action to perform on frame entries of the lookup stage, and in response to... Agent: Broadcom Corporation
20110271084 - Information processing system and information processing method: A disclosed information processing system includes a receiving node and a storing node, the receiving node includes an order information adding unit that adds first order information to operation instructions included in an operation instruction sequence, the first order information indicating an order among the operation instruction sequences and an... Agent: Fujitsu Limited
20110271085 - Parsing-enhacement facility: An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an... Agent: International Business Machines CorporationPrevious industry: Electrical computers and digital processing systems: memory
Next industry: Electrical computers and digital processing systems: support
RSS FEED for 20140710:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) patents we recommend signing up for free keyword monitoring by email.
Results in 0.48262 seconds