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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) October categorized by USPTO classification 10/11

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
10/27/2011 > 11 patent applications in 10 patent subcategories. categorized by USPTO classification

20110264888 - Dynamically reconfigurable systolic array accelorators: A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system.... Agent: Utah State University

20110264889 - Systems and methods for processing data: Systems, methods, and an article of manufacture for the reduction in process load experienced by a primary processor when executing an application by dynamically reassigning portions of the application to one or more secondary processors are shown and described. A second processing unit is queried for one or more characteristics.... Agent: Mirics Semiconductor Limited

20110264890 - Electronic chip and integrated circuit including such an electronic chip: The routing unit (110E) of at least one functional module, called a split routing unit, includes two routers (112E, 114E), called respectively a first-level router and a second-level router, which are connected to one another, where the first-level router is moreover connected to at least two routing connections, and where... Agent: Commissariat A L'energie Atomique Et Aux Ene. Alt.

20110264891 - Microprocessor that fuses mov/alu/jcc instructions: A microprocessor receives first, second, and third program-adjacent macroinstructions. The first macroinstruction moves a first operand to a first register from a second register. The second macroinstruction performs an arithmetic/logic operation using the first operand in the second register and a second operand in a third register to generate a... Agent: Via Technologies, Inc.

20110264892 - Data processing device: Provided is a data processing device (101) which can execute more number of instructions in parallel. The data processing device (101) includes: a first register file section (110) including plural registers; a second register file section (210) including plural registers associated with the respective registers of the first register file... Agent: National University Corporation Nara Institute Of Science And Technology

20110264893 - Data processor and ic card: The data processor includes: a memory device for storing a program compiled by a compiler; and CPU operable to fetch an instruction code included by a program stored in the memory device. Further, the data processor has a filter for judging an instruction code which the compiler never outputs to... Agent: Renesas Electronics Corporation

20110264894 - Branching processing method and system: A method is provided for controlling a pipeline operation of a processor. The processor is coupled to a memory containing executable computer instructions. The method includes determining a branch instruction to be executed by the processor, and providing both an address of a branch target instruction of the branch instruction... Agent:

20110264895 - Method and apparatus for performing multiply-add operations on packed data: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said... Agent:

20110264896 - Microprocessor that fuses mov/alu instructions: A microprocessor receives first and second program-adjacent macroinstructions of the instruction set architecture of the microprocessor. The first macroinstruction instructs the microprocessor to move a first operand to a first architectural register from a second architectural register. The second macroinstruction instructs the microprocessor to perform an arithmetic/logic operation using the... Agent: Via Technologies, Inc.

20110264897 - Microprocessor that fuses load-alu-store and jcc macroinstructions: A microprocessor receives first and second program-adjacent macroinstructions of the microprocessor instruction set architecture. The first macroinstruction loads an operand from a location in memory, performs an arithmetic/logic operation using the loaded operand to generate a result, and stores the result back to the memory location. The second macroinstruction jumps... Agent: Via Technologies, Inc.

20110264898 - Checkpoint allocation in a speculative processor: The embodiments described in the instant application provide a system for generating checkpoints. In the described embodiments, while speculatively executing instructions with one or more checkpoints in use, upon detecting an occurrence of a predetermined operating condition or encountering a predetermined type of instruction, the system is configured to determine... Agent: Oracle International Corporation

  
10/20/2011 > 11 patent applications in 10 patent subcategories. categorized by USPTO classification

20110258413 - Apparatus and method for executing media processing applications: An apparatus and method for executing media processing applications in a heterogeneous multicore system are provided. The media processing application executing apparatus includes a configuration deciding unit to decide a configuration for a combination of computational kernels and cores in which the computation kernels are to be executed. The computation... Agent: Samsung Electronics Co., Ltd.

20110258414 - Apparatus and method for processing data streams: A distributed architecture and method for maintaining the integrity of data streams within a multi-pipelined processing environment. The architecture comprising a communications network for carrying a plurality of data streams and a master processor adapted to process one or more messages in at least one of the data streams, the... Agent: Bae Systems PLC

20110258415 - Apparatus and method for handling dependency conditions: Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these... Agent: Sun Microsystems, Inc.

20110258417 - Power and throughput optimization of an unbalanced instruction pipeline: A method includes determining a rate of resource occupancy of a constituent stage of an unbalanced instruction pipeline implemented in a processor through profiling an instruction code. The method also includes performing data processing at a maximum throughput at an optimum clock frequency based on the rate of resource occupancy.... Agent:

20110258416 - Statically speculative compilation and execution: A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the speculative static information in an instruction set architecture of a processor, and executing a compiled computer program using the speculative static information, wherein executing supports... Agent: Bluerisc Inc., A Massachusetts Corporation

20110258418 - Load/move duplicate instructions for a processor: A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.... Agent:

20110258419 - Attaching and virtualizing reconfigurable logic units to a processor: In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled... Agent:

20110258420 - Execution migration: An execution migration approach includes bringing the computation to the locus of the data: when a memory instruction requests an address not cached by the current core, the execution context (current program counter, register values, etc.) moves to the core where the data is cached.... Agent: Massachusetts Institute Of Technology

20110258421 - Architecture support for debugging multithreaded code: Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with... Agent: International Business Machines Corporation

20110258422 - Microcomputer: There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing a program executed in user boot mode and corresponding endian information and a user area for storing a program executed in user mode and... Agent: Renesas Electronics Corporation

20110258423 - Computer processor and method with increased security policies: A computer processor 100 is provided which hides jump instructions, in particular condition jump instructions, from side-channels. The processor comprises a forward jump detector 254 for detecting a forward jump instruction having a jump target location which lies ahead and a jump inhibitor 262 for inhibiting an execution of the... Agent: Nxp B.v.

  
10/13/2011 > 4 patent applications in 4 patent subcategories. categorized by USPTO classification

20110252219 - Information processing apparatus: According to an aspect of the present invention, there is provided an information processing apparatus including: a first processor; a second processor that has an information processing capability and a power consumption higher than those of the first processor; a temperature monitoring module configured to acquire an operating temperature of... Agent:

20110252220 - Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits: A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field,... Agent: International Business Machines Corporation

20110252221 - Microcomputer and interrupt control method: A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch instruction code from an instruction memory in... Agent: Renesas Electronics Corporation

20110252222 - Event counter in a system adapted to the javacard language: The implementation of a counter in a microcontroller adapted to the JavaCard language while respecting the atomicity of a modification of the value of this counter, wherein the counter is reset by the sending to the microcontroller of an instruction to verify a user code by submitting a correct code,... Agent: Proton World International N.v.

  
10/06/2011 > 7 patent applications in 5 patent subcategories. categorized by USPTO classification

20110246746 - Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same: Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In... Agent:

20110246747 - Reconfigurable circuit using valid signals and method of operating reconfigurable circuit: A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node... Agent: Fujitsu Semiconductor Limited

20110246748 - Managing sensor and actuator data for a processor and service processor located on a common socket: Illustrated is a system and method that includes a processor and service processor co-located on a common socket, the service processor to aggregate data from a distributed network of additional service processors and processors both of which are co-located on an additional common socket. The system and method also includes... Agent:

20110246749 - Dynamic energy savings for a digital signal processor module: In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in... Agent:

20110246751 - Instruction and logic for processing text strings: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding... Agent:

20110246750 - Processing capacity on demand: Embodiments of the present invention relate to a system and method for providing processing capacity on demand. According to the embodiments, a processor package has a plurality of processing elements. One or more of the processing elements may be made active in response to increased demand for processing capacity based... Agent:

20110246752 - Emulating execution of an instruction for discovering virtual topology of a logical partitioned computer system: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology... Agent: International Business Machines Corporation

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