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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) September class, title,number 09/11

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
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09/29/2011 > 19 patent applications in 12 patent subcategories. class, title,number

20110238948 - Method and device for coupling a data processing unit and a data processing array: The present invention relates to a method of coupling at least one (conventional) unit processing data in a sequential manner, e.g. a CPU, von-Neumann-Processor and/or microcontroller, the (conventional) unit for data processing comprising an instruction pipeline, and an array for processing data comprising a plurality of data processing cells, e.g.... Agent:

20110238949 - Distributed administration of a lock for an operational group of compute nodes in a hierarchical tree structured network: Distributed administration of a lock for an operational group of compute nodes in a hierarchical tree structured network including assigning the root node of the operational group to send acknowledgments for lock requests, the root lock administration module comprising a module of automated computing machinery; receiving a lock request assigned... Agent: International Business Machines Corporation

20110238951 - Image forming apparatus, image forming system, and information generating method: s

20110238950 - Performing a scatterv operation on a hierarchical tree network optimized for collective operations: Performing a scattery operation on a hierarchical tree network optimized for collective operations including receiving, by the scattery module installed on the node, from a nearest neighbor parent above the node a chunk of data having at least a portion of data for the node; maintaining, by the scattery module... Agent: International Business Machines Corporation

20110238952 - Instruction fetch apparatus, processor and program counter addition control method: An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an... Agent: Sony Corporation

20110238953 - Instruction fetch apparatus and processor: An instruction fetch apparatus is disclosed which includes: a detection state setting section configured to set the execution state of a program of which an instruction prefetch timing is to be detected; a program execution state generation section configured to generate the current execution state of the program; an instruction... Agent: Sony Corporation

20110238954 - Data processing apparatus: Source code to be processed is analyzed and configuration data in implementing in accordance with each of plural implementation systems is created and is stored in a local memory of a DRP incorporating system. When execution of target processing is started, the implementation system determination processing calculates estimated processing time... Agent: Fuji Xerox Co., Ltd.

20110238955 - Methods for scalably exploiting parallelism in a parallel processing system: Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual threads of program execution are defined to solve the lowest-level sub-problems. The threads are grouped into one or more thread arrays,... Agent: Nvidia Corporation

20110238956 - Collective acceleration unit tree structure: A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within a collective tree. The input collective packet comprises a... Agent: International Business Machines Corporation

20110238958 - Data processing device: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines... Agent: Renesas Electronics Corporation

20110238957 - Software conversion program product and computer system: According to one embodiment, a software conversion program product having a computer readable medium including programmed instructions, wherein the instructions, when executed by a computer system including a host processor and one or more accelerator processors, causes the computer system to perform: analyzing input software and obtaining a compute intensity... Agent: Kabushiki Kaisha Toshiba

20110238959 - Distributed controller, distributed processing system, and distributed processing method: A distributed controller is connected to two or more processing elements and controls the two or more processing elements to execute distributed processing. The distributed controller comprises a plurality of control modules, each of which is connected to at least one other control module. The distributed controller determines a processing... Agent: Olympus Corporation

20110238960 - Distributed processing system, control unit, processing element, distributed processing method and computer program: A distributed processing system has a control unit and a plurality of processing elements and includes a control line through which control information is sent and received between the control unit and the processing elements, and a data line through which data to be processed is transmitted from at least... Agent: Olympus Corporation

20110238961 - System and method of instruction modification: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment... Agent:

20110238962 - Register checkpointing for speculative modes of execution in out-of-order processors: A mechanism is provided for generating a checkpoint for a speculatively executed portion of code. The mechanisms identify, during a speculative execution of a portion of code, a register renaming operation occurring to an entry in a register renaming table of the processor. In response to the register renaming operation... Agent: International Business Machines Corporation

20110238963 - Reconfigurable array and method of controlling the reconfigurable array: A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to... Agent:

20110238964 - Data processor: The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU... Agent: Renesas Electronics Corporation

20110238966 - Branch prediction method and branch prediction circuit for executing the same: A branch prediction method executed in a branch prediction circuit executes the branch instruction, the branch prediction method includes: a branch information storing process for storing the information in the first storage unit or the second storage unit; a process for determining on the basis of a branch condition set... Agent: Fujitsu Limited

20110238965 - Branch prediction method and branch prediction circuit performing the method: A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the memory in accordance with a result of determining whether or not a predicted branch has been taken, and determining an attribute of the... Agent: Fujitsu Limited

  
09/22/2011 > 6 patent applications in 6 patent subcategories. class, title,number

20110231632 - Semiconductor device: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation... Agent: Renesas Electronics Corporation

20110231633 - Operand size control: A data processing system 2 is provided with processing circuitry 8, 10, 12 as well as a bank of 64-bit registers 6. An instruction decoder 14 decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers 6. The... Agent: Arm Limited

20110231634 - System and method for grouping alternative possibilities in an unknown instruction path: A method, system and device is provided for processing digital data, for example, video, image, and media data. A dispatch unit may simultaneously issue a plurality of instructions to an execution unit. The instructions may correspond to different mutually exclusive outcomes of a common condition. A processor may determine the... Agent:

20110231635 - Register, processor, and method of controlling a processor: A processor and a processor control method which efficiently perform an operation on data using a register, are provided. The register may include a data type field and a data field. The processor may generate the data type bits and store the generated data type bits in the data type... Agent: Samsung Electronics Co., Ltd.

20110231636 - Apparatus and method for implementing instruction support for performing a cyclic redundancy check (crc): Techniques relating to a processor including instruction support for implementing a cyclic redundancy check (CRC) operation. The processor may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit configured to receive instructions that include a first instance of a cyclic... Agent:

20110231637 - Central processing unit and method for workload dependent optimization thereof: A central processing unit (CPU) adapted for use in a computing system, such as a personal computer or other processing apparatus. The CPU is implemented to perform hyper-threading (HT), and further enables switching between HT-enabled and HT-disabled modes on the fly (without rebooting the apparatus) based on, for example, performance... Agent: Ocz Technology Group, Inc.

  
09/15/2011 > 11 patent applications in 10 patent subcategories. class, title,number

20110225392 - Methods and apparatus for providing bit-reversal and multicast functions utilizing dma controller: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform... Agent: Altera Corporation

20110225393 - Device activating unit and cpu: A register circuit having a plurality of registers enabling the writing and reading of data by the specification of an address; a register controlling circuit monitoring data of a plurality of registers of the register circuit through the specification of an address, and writing, to a register pre-established in the... Agent: Yamatake Corporation

20110225395 - Data processing system and control method thereof: In a data processing system which includes a processor performing a processing in correspondence with a fetched instruction and a DRC capable of dynamically reconfiguring a circuit configuration in correspondence with configuration data, when the processor fetches the instruction, a configuration data decoder identifies whether or not the instruction is... Agent: Fujitsu Semiconductor Limited

20110225394 - Instruction breakpoints in a multi-core, multi-thread network communications processor architecture: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction... Agent:

20110225396 - Methods and apparatus for storing expanded width instructions in a vliw memory for deferred execution: Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a... Agent: Altera Corporation

20110225397 - Mapping between registers used by multiple instruction sets: A processor 4 is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction... Agent: Arm Limited

20110225398 - Advanced processor scheduling in a multithreaded system: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores... Agent:

20110225399 - Processor and method for supporting multiple input multiple output operation: A processor for supporting a MIMO operation and method of processing a MIMO instruction are provided. The MIMO operation supporting processor may include a scheduler and at least one functional unit. The scheduler may map multiple inputs of the MIMO instruction to a plurality of sequential input cycles, respectively, and... Agent: Samsung Electronics Co., Ltd.

20110225400 - Device for testing a multitasking computation architecture and corresponding test method: A device and method for testing a multitasking computation architecture is provided. Sequences of test instructions are generated corresponding to programming rules for the computation architecture. The execution of the instruction sequences is controlled so that the sequences are alternately executed within the computation architecture.... Agent: Stmicroelectronics (grenoble 2) Sas

20110225401 - Prefetching branch prediction mechanisms: A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action... Agent: International Business Machines Corporation

20110225402 - Apparatus and method for handling exception events: Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding... Agent: Arm Limited

  
09/08/2011 > 16 patent applications in 14 patent subcategories. class, title,number

20110219207 - Reconfigurable processor and reconfigurable processing method: A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated... Agent: Samsung Electronics Co., Ltd.

20110219208 - Multi-petascale highly efficient parallel supercomputer: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be... Agent: International Business Machines Corporation

20110219209 - Dynamic atomic bitsets: Embodiments of the present invention provide techniques, including systems, methods, and computer readable medium, for dynamic atomic bitsets. A dynamic atomic bitset is a data structure that provides a bitset that can grow or shrink in size as required. The dynamic atomic bitset is non-blocking, wait-free, and thread-safe.... Agent: Oracle International Corporation

20110219210 - System core for transferring data between an external device and memory: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the... Agent: Altera Corporation

20110219211 - Cpu core unlocking device applied to computer system: A CPU core unlocking device applied to a computer system is provided. The core unlocking device includes a CPU having a plurality of signal terminals and a core unlocking executing unit having a plurality of GPIO ports connected with the corresponding signal terminals of the CPU. The GPIO ports of... Agent: Asustek Computer Inc.

20110219213 - Instruction cracking based on machine state: A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set... Agent: International Business Machines Corporation

20110219212 - System and method of processing hierarchical very long instruction packets: A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is... Agent: Qualcomm Incorporated

20110219214 - Microprocessor having novel operations: A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating... Agent:

20110219215 - Atomicity: a multi-pronged approach: In a multiprocessor system with speculative execution, atomicity can be approached in several fashions. One approach is to have atomic instructions that achieve multiple functions and are guaranteed to complete. Another approach is to have blocks of code that are grouped to succeed or fail together. A system can incorporate... Agent: International Business Machines Corporation

20110219216 - Mechanism for performing instruction scheduling based on register pressure sensitivity: A mechanism for performing instruction scheduling based on register pressure sensitivity is disclosed. A method of embodiments of the invention includes performing a preliminary register pressure minimization on program points during a compilation process of a software program running on a virtual machine of a computer system. The method further... Agent:

20110219217 - System on chip breakpoint methodology: A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured to program the computing elements with task descriptors and the computing elements are configured to receive the task descriptors and to perform... Agent: Mobileye Technologies Ltd.

20110219218 - Distributed order orchestration system with rollback checkpoints for adjusting long running order management fulfillment processes: A computer-readable medium, computer-implemented method, and system are provided. In one embodiment, a rollback checkpoint for a step in an executable process is established, and the executable process is executed. A change request is received, and the step with the established rollback checkpoint is adjusted. Any subsequent steps of the... Agent: Oracle International Corporation

20110219219 - Semiconductor integrated circuit and register address controller: This invention provides with a semiconductor integrated circuit, comprising a register map that makes correspondence between a register to which a CPU accesses and an address which specifies the register, wherein the register map includes a plurality of register maps in which assignments of address bits are rearranged in correspondence... Agent: Panasonic Corporation

20110219220 - Link stack repair of erroneous speculative update: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the... Agent: Qualcomm Incorporated

20110219221 - Dynamic warp subdivision for integrated branch and memory latency divergence tolerance: Dynamic warp subdivision (DWS), which allows a single warp to occupy more than one slot in the scheduler without requiring extra register file space, is described. Independent scheduling entities also allow divergent branch paths to interleave their execution, and allow threads that hit in the cache or otherwise have divergent... Agent:

20110219222 - Building approximate data dependences with a moving window: Mechanisms for building approximate data dependences using a moving look-back window are provided. The mechanisms track dependence information for memory accesses over iterations of execution of a portion of code. The mechanisms receive a memory access of an iteration of the portion of code, the memory access having an address... Agent: International Business Machines Corporation

  
09/01/2011 > 7 patent applications in 7 patent subcategories. class, title,number

20110213946 - Parallel computing system and communication control program: A parallel computing system includes a plurality of processors multi-dimensionally commented by an interconnection network, wherein each of the processors in the parallel computing system determines, in dimensional order, communication channels to other processors in the interconnection network, each of the processors sets, as relative coordinates of destination processors with... Agent: Fujitsu Limited

20110213947 - System and method for power optimization: A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the... Agent:

20110213948 - Efficient processor apparatus and associated methods: An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than the set of instructions in the first memory. An instruction in the set of instructions in the first memory is... Agent:

20110213949 - Methods and apparatus for optimizing concurrency in multiple core systems: Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. Tag logic may be located within the interconnect, such as located in an agent, and configured to assign different interconnect tag identification numbers... Agent: Sonics, Inc.

20110213950 - System and method for power optimization: A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the... Agent:

20110213951 - Storing branch information in an address table of a processor: Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch... Agent: International Business Machines Corporation

20110213952 - Methods and apparatus for dynamic instruction controlled reconfigurable register file: A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For... Agent: Altera Corporation

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